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Browse Prior Art Database

Fast Effective Address Generator

IP.com Disclosure Number: IPCOM000115119D
Original Publication Date: 1995-Mar-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 90K

Publishing Venue

IBM

Related People

Bishop, RH: AUTHOR [+3]

Abstract

In high-speed microprocessors, cycle time is limited by a number of critical timing paths. One of the most difficult paths to make fast enough involves the generation of the Effective Address (EA) of a load or store instruction. For example, an instruction of the form: lwz RT, D(RA) requires that the value in RA be added to the displacement value D to produce the effective address.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Fast Effective Address Generator

      In high-speed microprocessors, cycle time is limited by a
number of critical timing paths.  One of the most difficult paths to
make fast enough involves the generation of the Effective Address
(EA) of a load or store instruction.  For example, an instruction of
the form:
  lwz  RT, D(RA)
  requires that the value in RA be added to the displacement value D
to
produce the effective address.

      The high order bits of the effective address are generally sent
to a Translation Lookaside Buffer (TLB) and/or segment register to
produce the real page number (high order bits of the real address).
The real page number is used in the cache tag compare to determine if
the cache access was a hit or miss.

      The simple method is illustrated in Fig. 1.  With this method,
two operands in the reservation station of the load/store unit are
always added with a 32-bit adder.  The output of this adder directly
feeds the memory translation logic.

      This simple method is fast, but limits the throughput of
instructions in the load/store unit.  If a cache miss or resource
conflict occurs, the load/store unit may not be signalled until the
following cycle.  By this time, another instruction may have arrived
in the reservation station, overwriting the previous instruction.
Possible solutions to this problem are:
  o  Delay the new instruction until it is known that the old
      instruction will not be stalled.  This has the side effect of
      reducing the load/ store unit to an unacceptable minimum of 2
      cycles per instruction.
  o  Save the old instruction in a different register, and mux it in
      to the reservation station if the memory access needs to be
      retried.  This requires a control mechanism that also saves the
      new instruction before the old instruction overwrites it, and
      complicates the reservation station.  This method introduces
new
      critical timing paths, and proved too slow to work on our
project.
 ...