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Fan Good Circuit with Locked Rotor Sense

IP.com Disclosure Number: IPCOM000115129D
Original Publication Date: 1995-Mar-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 96K

Publishing Venue

IBM

Related People

Patterson, BE: AUTHOR

Abstract

Described is a hardware implementation to provide a fan good signal for power supplies or other applications requiring fan sensing. The implementation provides circuitry to prevent false fan status if the fan fails due to locked rotor conditions.

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This is the abbreviated version, containing approximately 52% of the total text.

Fan Good Circuit with Locked Rotor Sense

      Described is a hardware implementation to provide a fan good
signal for power supplies or other applications requiring fan
sensing.  The implementation provides circuitry to prevent false fan
status if the fan fails due to locked rotor conditions.

      The Figure shows the circuit representation for sensing a fan
and generating a positive fan good signal.  The fan good circuit
consists of bi-polar transistors Q1 and Q2, resistors R1 through R11,
diode D1, voltage comparators ZM2 and ZM3, operational amplifier ZM1,
and capacitor C1.  Bias voltage Vcc1 represents a positive source
voltage for the fan, +12V as an example, and Vcc2 represents a
positive source voltage for the circuitry, +5V as an example.

      The fan good circuit described functions in six modes: Normal
Fan Operation; Fan Open during Start; Fan Shorted during Start; Fan
Opening (Shorting) after Starting; Fan Locked Rotor during Start-up;
and Fan Locked Rotor after Start-up.

      During normal fan operation, the current flowing through the
fan and R1 is converted to a voltage by R1 at the R1, R2 node.  This
voltage is amplified by non-inverting amplifier ZM1 to establish
output voltage Vf.  The gain of the amplifier is established by R3
and R4.  Voltage Vf is thus proportional to the voltage across R1 and
is a reflection of the current flowing through the fan.

      Voltage Vf is compared to reference voltages Vra and Vrb by
comparators ZM2 and ZM3.  Resistor network R5, R6, and R7 is used to
develop the reference levels Vra and Vrb.  If Vf is within the
allowable window of Vra and Vrb comparators ZM2 and ZM3 turn-off
(High output state).  This allows current to flow through pull-up
resistor R8 and charge capacitor C1.  When the voltage across C1
raises above the forward voltage drop of diode D1 and the Q1 b-e
junction voltage (Q1 base to emitter) current flows into the base of

Q1 turning Q1 on.  When Q1 turns on, current is pulled through R10
which turns off Q2 to provide a fan "good", high output signal.

      During start-up, if the fan is open Vf will be at zero (0)
volts.  When Vf is compared to Vrb, Vrb will be higher which turns on
comparator ZM3 (Low or current sink output state).  Thus no current
flows into C1, through D1, or into the base of Q1.  Q1 remains off
which allows current to flow through R10 into the base of Q2 turning
Q2 on.  With Q2 on, a low or fan "bad" signal is provided.

      During start-up, if the fan is short...