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Real-Time Self-Granting, Centrally Directed Distributed Arbitration with Fairness

IP.com Disclosure Number: IPCOM000115146D
Original Publication Date: 1995-Mar-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 230K

Publishing Venue

IBM

Related People

Marenin, G: AUTHOR

Abstract

Present channel bus arbitrations (e.g., PS/2* Micro Channel*, RS/6000* SIOBus, FDDI Generic Adapter Bus, VMEBus, E/ISA, Intel, PCI, VETA, Futurebus+, etc.) require many paired bus priority lines or slow daisy chains or arbitration delay times. To approach maximum bandwidth, large data bursts are needed with costly latency buffers to hide the arbitration, addressing, latency and tri-state turnaround overhead cycles. This creates hogging of the bus that is not solved by still more fairness hardware that only treats the symptoms and not the cause of the problem.

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This is the abbreviated version, containing approximately 22% of the total text.

Real-Time Self-Granting, Centrally Directed Distributed Arbitration
with Fairness

      Present channel bus arbitrations (e.g., PS/2* Micro Channel*,
RS/6000* SIOBus, FDDI Generic Adapter Bus, VMEBus, E/ISA, Intel, PCI,
VETA, Futurebus+, etc.) require many paired bus priority lines or
slow daisy chains or arbitration delay times.  To approach maximum
bandwidth, large data bursts are needed with costly latency buffers
to hide the arbitration, addressing, latency and tri-state turnaround
overhead cycles.  This creates hogging of the bus that is not solved
by still more fairness hardware that only treats the symptoms and not
the cause of the problem.  This invention solves all the above
drawbacks by continuous (automatic preemption), two cycle (no slow
open collector lines), self-granting (faster with saved acknowledge
lines), centrally directed (timed with instant fairness overrides)
distributed (fault-tolerant with saved addressing and dead cycles)
arbitration approaching maximum bus bandwidth with shorter data
packet bursts.

      Current Practice - Today's support of multiple bus masters for
Direct Memory Access (DMA) or peer to peer I/O transfers takes many
cycles and control lines to accomplish the priority arbitration to
determine the winner.  In many cases this time increases latencies
and usually reduces the bandwidth.  Further bandwidth loss is due to
the addressing cycles and to the associated bus turnaround dead
cycles.  To compensate, costly large burst buffers are used and high
priority short transfers become inefficient and the architecture is
not real-time.  Complexity is further increased by requiring
elaborate fairness preemptions to avoid parasitic hogging by the bus
masters.  This just slightly relieves the symptoms instead of
eliminating the root of the problem.

      This disclosure provides for the sharing of the total bus
bandwidth on real-time basis by an efficient fairness algorithm that
can be modified as desired to suit specific applications.  This
innovation first eliminates the wasted arbitration cycles and second,
permits a new bus master to be granted every two cycles.  Therefore,
short data transfers from different bus masters can approach the same
maximum bandwidth (as a single address non-sliced bus master data
bursts) without the need of costly data buffering and preempting
hardware.  There is also no need for the Arbitrate/Grant, Busy,
Burst, Command, Preempt, or all the Memory Matched interface signals.
All this increases performance and reduces the attachment costs.

      Each arbitration level (AB bit that can be time shared or
encoded) is a unidirectional totem-pole line including a single
highest priority level that is the Arbitration Control and Clock
(ACC) immediate priority bus mastership override and the 2 cycle
synchronization timing signal.  Every two cycles a new master-elect
is determined and any such last master-elect (automatic preemption)
becomes the next operat...