Browse Prior Art Database

60x/PCI Bus Memory Controller Design with Cache Coherency

IP.com Disclosure Number: IPCOM000115149D
Original Publication Date: 1995-Mar-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 94K

Publishing Venue

IBM

Related People

Bui, HQ: AUTHOR [+4]

Abstract

Disclosed is a memory controller design for a desktop PowerPC* system. The memory controller interfaces with both the PCI bus and the 60x (processor) bus, and maintains coherency with both the L1 cache and the L2 cache.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

60x/PCI Bus Memory Controller Design with Cache Coherency

      Disclosed is a memory controller design for a desktop PowerPC*
system.  The memory controller interfaces with both the PCI bus and
the 60x (processor) bus, and maintains coherency with both the L1
cache and the L2 cache.

      A desktop PowerPC system requires a memory controller design
that interfaces with both the PCI bus and the 60x bus while
maintaining coherency with both L1 and L2 caches.  This is achieved
by initiating a memory cycle access based only on the 60x bus for
both 60x bus and PCI bus mastership, and inserting a wait state for
snoop detection.

      The Figure illustrates a memory controller state machine
implementation that satisfies the requirements described above.

Signal descriptions are as follows:
  TS_              60x bus transfer start.  When active low it
                    indicates the 60x address is valid on the bus.
  CPU_A0           60x most significant address bit.  When active low
                    it indicates a memory address cycle.
  ARTRY_           60x bus address retry.  When active low it
indicates
                    a snoop hit from either L1 (60x) or L2 cache.
  CACHE_PS_        L2 cache presence.  When active low it indicates
the
                    presence of the L2 cache.
  CACHE_HIT_       L2 cache hit.  When active low it indicates a tag
                    hit on the current 60x address bus, thus
requiring a
                    memory access to abort.
  FRAME_           PCI address validation when active low.
  IRDY_            PCI initiator ready.  When active low it indicates
                    that it is ready for data transfer on the PCI
bus.
  TRDY_            PCI target ready.  When active low it indicates
that
                    it is ready for data transfer.
  PCI_SEL_         PCI or CPU mastership.  When asserted low it
                    indicates PCI mastership; when asserted high it
                    indicates CPU mastership.
  MEM_RDY_         Memory ready.  When active low it indicate...