Browse Prior Art Database

P1394 Link Layer Read Request Linked List Mechanism

IP.com Disclosure Number: IPCOM000115155D
Original Publication Date: 1995-Mar-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 6 page(s) / 213K

Publishing Venue

IBM

Related People

Hoch, G: AUTHOR [+6]

Abstract

Disclosed is a dynamic appendable Read Request Linked List mechanism implemented in a P1394 Link Chip, which interfaces to a Peripheral Component Interconnect (PCI) bus as the system bus and to the PHY module for P1394 bus accesses. The PHY is a hybrid digital and analog module to which the Link Chip interfaces for getting on the P1394 bus. This mechanism allows the software to append P1394 Read Request packets dynamically into an active linked list for continuous operation without race conditions. The Link Chip automatically paces Read Request packets by allowing at most two outstanding Read Request packets to be pending and by correlating the returned (Read Response) packets.

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P1394 Link Layer Read Request Linked List Mechanism

      Disclosed is a dynamic appendable Read Request Linked List
mechanism implemented in a P1394 Link Chip, which interfaces to a
Peripheral Component Interconnect (PCI) bus as the system bus and to
the PHY module for P1394 bus accesses.  The PHY is a hybrid digital
and analog module to which the Link Chip interfaces for getting on
the P1394 bus.  This mechanism allows the software to append P1394
Read Request packets dynamically into an active linked list for
continuous operation without race conditions.  The Link Chip
automatically paces Read Request packets by allowing at most two
outstanding Read Request packets to be pending and by correlating the
returned (Read Response) packets.

      Fig. 1 is a block diagram illustrating the format of a single
Read Request packet.  The second entry from the last is the system
memory address for the data in the Read Response packet returned by
the initiator.  The entry before the last entry is the control word,
and
the last entry is the next address, of the next transmit data block.

Fig. 2 is a Table describing meanings of the fields in the control
word of Fig. 1.

      Fig. 3 is a block diagram showing the Read Request Linked List
in the system memory.  The control and next address words of the next
Read Request data block are designed to reside in the preceding data
block, so that the Link Chip can set up Direct Memory Access (DMA)
for fetching the next Read Request data block.  The control and next
address words of the first Read Request reside in the Link Chip.

      Fig. 4 is a block diagram showing the format of the Read
Request Packet Control Register, which resides in the Link Chip.
This register is used to control how data in the Transmit Buffer is
to be formatted when it is sent out on the P1394 bus after fetching
from the Read Request Linked List.  The Read Request Packet Control
Register is the control register for the first Read Request data
block of the Linked List in system memory.  This register is replaced
by the respective control word of the data block shown in Fig. 1,
except for the Start (STR) and Status (STS) bits.

Fig. 5 is a table describing meanings of the fields in the control
word of Fig. 4.

      A 32-bit Read Request Packet Address Register is used to hold
the address of the first Read Request block of the Read Request
Linked List in system memory.  This register is updated to the next
Read Request block address after the current data block is fetched
into the Link Chip.

      Referring again to Fig. 3, in the first step of a Read Request
data linked list operation, software sets up the Read Request Linked
List in system memory, writing the memory address of the first Read
Request data block to the Read Request Packet Address Register.  The
software then programs the Read Request Packet Control Register with
the desired functions and sets the STR (Start) bit to '1.'

      In...