Browse Prior Art Database

Peripheral Component Interconnect Target/60x Snoop Cycle

IP.com Disclosure Number: IPCOM000115161D
Original Publication Date: 1995-Mar-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 87K

Publishing Venue

IBM

Related People

Bui, HQ: AUTHOR [+5]

Abstract

Disclosed is a method to maintain cache coherency within the L1 and L2 caches during PCI-to-memory cycles in a PowerPC* desktop system.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 54% of the total text.

Peripheral Component Interconnect Target/60x Snoop Cycle

      Disclosed is a method to maintain cache coherency within the L1
and L2 caches during PCI-to-memory cycles in a PowerPC* desktop
system.

      For PCI-to-memory cycles on a PowerPC desktop system, cache
coherency within the L1 and L2 caches must be maintained.  This is
accomplished through generation of snoop cycles on the 60x
(processor) bus for each PCI-to-memory cycle.  Fig. 1 illustrates
this implementation.

      A snoop cycle is generated on the 60x bus for every
PCI-mastered data transfer, including those during a burst
transaction.  A snoop cycle is generated on the 60x bus the second
PCI cycle after FRAME_ is asserted for each PCI master single-beat
cycle; in addition, a snoop cycle is generated on the 60x bus the
second CPU clock after TRDY_ is asserted if FRAME_ remains active to
indicate a PCI master burst transaction.

      For each snoop cycle, the PCI address is asserted on the 60x
bus by the signal PCI_AD_SEL_.  The 60x master snoop state machine
will assert TS_ for one CPU clock.  AACK_ is asserted on the second
CPU clock after TS_ is asserted.  Then on the third CPU clock after
TS_ is asserted, AACK_ will be de-asserted and ARTRY_ will be
sampled.  See Fig. 2 for a timing diagram of a PCI single-beat
transfer.

      Fig. 3 shows a timing diagram for a PCI burst transaction.  The
first snoop cycle is generated on the 60x bus within the second PCI
clock that FRAME_...