Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

High-Speed Asynchronous Interface Design

IP.com Disclosure Number: IPCOM000115168D
Original Publication Date: 1995-Mar-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Arimilli, RK: AUTHOR

Abstract

In computer systems, when an operation is transferred across a clock boundary, a certain amount of latency is incurred due to the synchornization time from one clock synchronous logic to another. This papers describes a method in which this latency can be reduced with minimal hardware.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 72% of the total text.

High-Speed Asynchronous Interface Design

      In computer systems, when an operation is transferred across
a clock boundary, a certain amount of latency is incurred due to the
synchornization time from one clock synchronous logic to another.
This papers describes a method in which this latency can be reduced
with minimal hardware.

      Fig. 1 shows a traditional latch to latch interface for the
transfer of a control signal, OP1.  Note that OP1 is captured by a
different clock, CLOCK2.  In most asynchronous interfaces, OP1_D, is
typically valid and stable early in the CLOCK1 cycle.  Furthermore,
since most chip designs make worst case delay assumptions, the OP1_D
is almost always valid the entire CLOCK1 cycle prior to OP1.  Fig. 2
shows a means of fowarding a valid and stable OP1_D to the OP1_NEW
signal by taking advantage of chip tracking delays.  Basically, DLY1
is slightly greater than the worst case, clock to output and
combinational logic delay of OP1_D.  The DLY2 is slightly greater
than minimum "set" pulse width requirement of the asynchronous
Set/Reset (SR) latch.  Note that this SR latch is reset dominant.
With this circuit, CLOCK2 will sample an earlier version of OP1,
OP1_NEW, almost a full CLOCK1 cycle earlier.  Finally, Fig. 2 shows a
means of increasing the sample rate of CLOCK2 by sampling OP1_NEW on
the rising and falling edge of CLOCK2.  This reduces the average
latency by another quarter of a CLOCK2 cycle.  (This also assumes
that CLOCK...