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Browse Prior Art Database

Floor Planning for a High Speed Digital Filter

IP.com Disclosure Number: IPCOM000115176D
Original Publication Date: 1995-Mar-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 146K

Publishing Venue

IBM

Related People

Cukier, M: AUTHOR

Abstract

A floor planning technique for digital filters or other repetitive circuits is provided. This method has been successfully experimented, and leads to substantial speed improvement.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

Floor Planning for a High Speed Digital Filter

      A floor planning technique for digital filters or other
repetitive circuits is provided.  This method has been successfully
experimented, and leads to substantial speed improvement.

      In present CMOS LSI circuits, placement and routine programs
offer automatic floor planning to designers.  In order to reach high
speed circuits, the time transfer in wiring has to be decreased as it
is the main contributor for the overall delay.  Automatic tools have
limited performance, and a skilled designer can not tune the
parameters of the program to achieve the desired speed.  Therefore a
method for high speed repetitive circuit is proposed.  Following are
the four 4 steps of the method which intends to solve this issue:
  1.  Logical optimization - In this first step the designer reduces
       the number of logical layers, and simulates its design with
       "estimated" values of circuits delays.
  2.  Block layout optimization - A "design-of-experiments" model is
       used to determine a set of five or six parameters.  The
       parameters are then combined together with successive values
to
       form n test patterns.  A placement and wiring operation is
       performed for each pattern, and n circuit delays are measured.
       Then the parameters are tuned until the delay in one block
fits
       with the expected target.

    In our application, five parameters were chosen which are:
  o  length of rectangular area
  o  width  of rectangular area
  o  overlap factor
  o  congestion factor
  o  vertical wiring factor
  3.  Define a matrix of placement - The LSI circuit is parted into
       islands which are functional entities.  A multiplier is an
       island.  The total area of the chip is divided into squares.
If
       the total number of cells of the LSI is N, the total number of
       squares is S, and if the number of cells of the island is n,
then
       the island occupies a surface of <0.85 times n time...