Browse Prior Art Database

Diagnostic Method for a Buffered Remote Interface

IP.com Disclosure Number: IPCOM000115190D
Original Publication Date: 1995-Mar-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 131K

Publishing Venue

IBM

Related People

Cohen, MP: AUTHOR [+4]

Abstract

Disclosed is a comprehensive diagnostic mode of operation enabling high speed parallel port data paths and interface state machines to be validated without requiring any participation from the remote attached device. This method enables diagnostics to be run as a periodic operation during run time, since the procedures are transparent to the external interface. Critical circuit data paths and interface state machines are exercised without sending any data or control information over the parallel port connector.

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This is the abbreviated version, containing approximately 52% of the total text.

Diagnostic Method for a Buffered Remote Interface

      Disclosed is a comprehensive diagnostic mode of operation
enabling high speed parallel port data paths and interface state
machines to be validated without requiring any participation from the
remote attached device.  This method enables diagnostics to be run as
a periodic operation during run time, since the procedures are
transparent to the external interface.  Critical circuit data paths
and interface state machines are exercised without sending any data
or control information over the parallel port connector.

      Fig. 1 shows the bit designations of a parallel port, POS Port
2, through which this method is implemented.  The values shown below
the register indicate that all of these bits are set to zero at
power-on reset, except for Bit 1, which is set to one.  Bit 5, when
set to a one level, enables the diagnostic mode of operation.  Bits
7, 6, and 4 are reserved.  Their values may be preserved by reading
and rewriting.  When Bit 3 is set to one, parity is generated and
checked across the parallel port connector.  When Bit 2 is set to
one, chip data parity support across the Micro Channel* is enabled.
When Bit 1 is set to one, the parallel port arbitration abides by
Micro Channel fairness.  When Bit 0 is at zero, the parallel port
interface is disabled for the master sleep function.

      Fig. 2 is the parallel port extended mode I/O register map.  In
order to isolate the remote attached device from the controller in
the diagnostic mode, the on-chip and off-chip buffers for the Port
data and control signals are disabled.  During normal operation, the
transmit mode transfer of data to the attached device is controlled
by the interface control signals between the port controller and the
attached device.  In the diagnostic mode, the flow of data through
the chip data paths is controlled by I/O reads of the parallel data
register associated with the port.  Other aspects of the controller
operation are identical to transmit mode operation during normal
operation of the circuit.

      Fig. 3 shows the data paths provided in the diagnostic mode.  A
parallel port is connected to the Micro Channel 10 through a
read/write multiplexor 12.  Data is read from the SCB write list data
buffer, a defined area of memory, into the chip.  The data is then
transferred on the internal data paths of the chip through the FIFO
buffer 14 and parallel data register 16 by various state machines.
The data is then paced through the data path and read out of the chip
by doing a sequence of I/O reads to parallel data register 16.  The
data in the write list data buffer is configured with diagnostic
patterns, such as walkin...