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Browse Prior Art Database

Compact Level-Sensitive Scan Design Shadow Latch for Transparent Latch Design Style

IP.com Disclosure Number: IPCOM000115197D
Original Publication Date: 1995-Mar-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 8 page(s) / 245K

Publishing Venue

IBM

Related People

Donahue, JD: AUTHOR

Abstract

Level-Sensitive Scan Design (LSSD) enables functional and fault simulation of a monolithic integrated circuit by creating a scan path traversing all latches on chip. When edge-based master-slave flip-flops are used in a design, little overhead is incurred. However, for designs employing transparent latches, the penalty for LSSD may be 100%, i.e., the addition of a latch for scan purposes for each latch needed functionally on the chip.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 29% of the total text.

Compact Level-Sensitive Scan Design Shadow Latch for Transparent
Latch Design Style

      Level-Sensitive Scan Design (LSSD) enables functional and fault
simulation of a monolithic integrated circuit by creating a scan path
traversing all latches on chip.  When edge-based master-slave
flip-flops are used in a design, little overhead is incurred.
However, for designs employing transparent latches, the penalty for
LSSD may be 100%, i.e., the addition of a latch for scan purposes for
each latch needed functionally on the chip.

      This disclosure presents a more compact latch which is used to
implement the LSSD scan path.

      Level-Sensitive Scan Design enables functional and fault
simulation of a monolithic integrated circuit by creating a scan path
connecting all latches on chip.  When edge-based master-slave
flip-flops are used in a design, little overhead is incurred.
However, for designs employing transparent latches, the penalty for
LSSD may be 100%, i.e., the addition of a latch for scan purposes for
each latch needed functionally on the chip.

      Transparent Latch design style is characterized by the use of
latches rather than flip-flops.  A flip-flop typically will be
constructed from a master and slave latch.  When the clock input is
low the master is loaded with incoming data, and when the clock input
goes high the slave latch latches the master latch's output and
simultaneously drives its output.  This flip-flop delays the
transition
of incoming signals until shortly after the rising edge of its clock.

      In Fig. 1 "Transparent Latch Style", L1 and L2 clocks are shown
driving three stages of latches.  Between each stage is combinatorial
logic (no latches).

      A typical method for adding LSSD to the previous Figure is
depicted in Fig. 2 "Transparent Latch Style with LSSD Shadows".  In
this Figure, "shadow" latches have been added to each transparent
latch depicted in Fig. 2.  The shadow latch guarantees that each
latch in the scan path consists of a standard master/slave Scan
Register Latch (SRL), although only the transparent latch was
required functionally by the circuit.

      Since the shadow latch has no purpose in the functionality of
the circuit other than to connect the scan path for LSSD, we'd like
to minimize the size of this shadow latch.  Because the serial scan
path is used in a carefully controlled manner, some circuit
optimizations
can be applied to this latch that might not be applicable to the
latch
used functionally in the circuit.  This disclosure presents a denser
latch that can be used for the LSSD shadow latch.

      Fig. 3 "Typical C1 Latch" depicts a typical implementation of
the C1 latch shown in Fig. 3 "Typical C1 Latch".  This latch works as
follows.  Normal data arrives on the D1 input and is clocked into
Latch 1 if C1 is asserted and C1_B is deasserted.  The logical
inversion of the data clocked into Latch 1 appears immediately on the
output...