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Arbitration Circuit for a Personal Computer Memory Card Internaional Association Card

IP.com Disclosure Number: IPCOM000115198D
Original Publication Date: 1995-Mar-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 76K

Publishing Venue

IBM

Related People

Kam, PK: AUTHOR

Abstract

The arbitration circuit described in this article is a three-way arbitration circuit. It uses two timing slots to sample three access initiators.This ensures the arbitration can be done within 20 to 30ns with a fixed system clock of 25Mhz. The restricted timing is needed because the PCMCIA standard requires the 'Wait' signal must be returned within 35ns after a command is issued. 'Wait' signal is generated after arbitration is done.

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Arbitration Circuit for a Personal Computer Memory Card Internaional
Association Card

      The arbitration circuit described in this article is a
three-way arbitration circuit.  It uses two timing slots to sample
three access initiators.This ensures the arbitration can be done
within 20 to 30ns with a fixed system clock of 25Mhz.  The restricted
timing is needed because the PCMCIA standard requires the 'Wait'
signal must be returned within 35ns after a command is issued.
'Wait' signal is generated after arbitration is done.

      Whenever there is a device( such as a memory or a local bus)
that can be accessed by many other devices (such as a CPU, DMA
Controller etc.), it requires an arbitrator (an arbitration circuit)
to direct the traffic in order to avoid access conflicts.

      Referring to Fig. 1, the arbitration circuit described in this
article has three devices:  namely the host system, the local DMA
controller and the DRAM refresh which must access the DRAM through a
single local bus.  There are two time slots, one for the HOST_REQ at
the falling edge of the clock (25Mhz), one for the DMA or Refresh at
the rising edge of the clock.  Flip Flop B is called Grant1 which
will be set if the Host_req is present and the Grant2 FF D is not set
at the falling edge of the clock.  FF D is called Grant2 which will
be set if DMA or Refresh is present and Grant1 is not set at the
rising edge of the clock.  If Grant2 is set, and if the JKFF G is
also set, th...