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Removing Self Test Delay from Boundary Scan Drivers

IP.com Disclosure Number: IPCOM000115201D
Original Publication Date: 1995-Mar-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Itskin, RC: AUTHOR [+4]

Abstract

With large ASIC designs it is necessary to include self test logic on the chip. This self test logic needs to control the internal latches and the receivers and drivers. However, to control the off chip drivers the self test logic inserts added delay that could cause timing problems.

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This is the abbreviated version, containing approximately 58% of the total text.

Removing Self Test Delay from Boundary Scan Drivers

      With large ASIC designs it is necessary to include self test
logic on the chip.  This self test logic needs to control the
internal latches and the receivers and drivers.  However, to control
the off chip drivers the self test logic inserts added delay that
could cause timing problems.

      The self test logic creates a signal that is used to disable
the chip's drivers by deactivating the enable signal.  This signal
must be multiplexed with each driver's functional enable signal which
causes part of the extra delay.  Plus for Boundary Scan drivers there
needs to be a latch type block sourcing the driver enable pin.  The
multiplexor is not a latch type block so one needs to be added
between the multiplexor and the driver enable pin.  This special
latch type block looks like a latch for testability purposes, but
passes the enable signal through during normal operation.  The delay
of the special latch causes most of the timing delay problem.

      This solution will remove the self test delay by utilizing
established testability features that exist for chips today.  The
chip already requires inputs to disable the drivers and receivers.
These inputs are typically tied inactive when the chips are attached
to planar boards.  Instead of multiplexing the self test disable with
the functional enables for each driver, the self test disable signal
is sent off chip and fed back into the driver inhibit sig...