Browse Prior Art Database

High Utilization and Reliability Memory Bit Steering Method

IP.com Disclosure Number: IPCOM000115206D
Original Publication Date: 1995-Mar-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 136K

Publishing Venue

IBM

Related People

Qureshi, AZ: AUTHOR

Abstract

Disclosed is a method of performing DRAM Memory bit steering that maximizes memory reliability and better utilizes the extra bits in an ECC code word. This is achieved by performing bit steering on a module basis using the DRAM Bank Select decodes. The data controllers can determine which bit in which particular bank is bad and therefore steer ONLY one bank. This allows multiple locations to be "bit" or "module" steered.

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High Utilization and Reliability Memory Bit Steering Method

      Disclosed is a method of performing DRAM Memory bit steering
that maximizes memory reliability and better utilizes the extra bits
in an ECC code word.  This is achieved by performing bit steering on
a module basis using the DRAM Bank Select decodes.  The data
controllers can determine which bit in which particular bank is bad
and therefore steer ONLY one bank.  This allows multiple locations to
be "bit" or "module" steered.

      To accomplish this method of bit steering, the data control
chips will need to keep track of the bank selects every time the main
memory is accessed.  In read operations, the bit steering multiplexer
used to multiplex the spare bits will select the normal path unless
bit steering is required.  Write operations use an n-wide multiplxer
(where n is the memory data bus width) to multiplex any of the actual
memory data bits and write it to memory.

      To implement this method, a log register is required to each
memory bank which keeps track of the frequency of soft ECC errors in
that particular bank ONLY.  The only time bit steering will fail if a
bad location is detected in the same memory bank which has already
been steered.  The probability of such an error is extremely low and
hence overall system reliability is dramatically increased (Figs. 1
and 2).

      This method can be used with any kind of ECC memory controller
designs and can be applied to multipl...