Browse Prior Art Database

Interface Signal Sharing

IP.com Disclosure Number: IPCOM000115221D
Original Publication Date: 1995-Apr-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 85K

Publishing Venue

IBM

Related People

Wolford, BJ: AUTHOR

Abstract

A method for combining two dependent interface signals onto a single signal line is disclosed. For systems having a fixed or limited number of interface signal lines available to provide multiple control signals, and thus eliminating the desired level of direct control over critical signals, a means is presented which allows such a system to utilize the existing interface to maximize system control of those signals.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Interface Signal Sharing

      A method for combining two dependent interface signals onto a
single signal line is disclosed.  For systems having a fixed or
limited number of interface signal lines available to provide
multiple control signals,  and thus eliminating the desired level of
direct control over critical signals, a means is presented which
allows such a system to utilize the existing interface to maximize
system control of those signals.

      It is desirable for a system to have complete control of DRAM
timings in a memory subsystem employing such.  Presently, systems
provide RAS, CAS, and ADDRESS which are latched and passed directly
to the DRAMs thus providing the system with the flexibility to change
the timing relationships of these control signals.  Other critical
DRAM signals (i.e, Toggle, R/W, etc.) are generated by the subsystem
support logic and have fixed timing relationships relative to RAS,
CAS, etc. and therefore cannot be moved relative to those signals.
Generation of DRAM control signals in this manner limits the systems
capability to COMPLETELY control the DRAM timings should timing
changes be necessary or desired.

      A system  whose interface is fixed  does not have the
additional signal lines necessary to provide all the necessary
control signals (i.e., Toggle, R/W, etc.).  For example, a system
which employs a memory subsystem utilizing Page mode DRAMs would not
have the additional interface signal lines necessary to provide the
Toggle signal should it decide to use a memory subsystem utilizing
Toggle mode DRAMs.

      Additional control signals can be placed on an existing
interface (making a costly interface change unnecessary...