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Hardware Assisted Wire Test for Standard Direct Random Access Memories and Daughter Cards

IP.com Disclosure Number: IPCOM000115224D
Original Publication Date: 1995-Apr-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 99K

Publishing Venue

IBM

Related People

Haselhorst, KH: AUTHOR [+2]

Abstract

A method for hardware testing of Direct Random Access Memories (DRAMs) and DRAM connections during Initial Program Load (IPL) is disclosed. It will run a fast check and detect most open or stuck conditions as well as some shorted conditions of the data and control lines to the DRAMs in a memory subsystem.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Hardware Assisted Wire Test for Standard Direct Random Access Memories
and Daughter Cards

      A method for hardware testing of Direct Random Access Memories
(DRAMs) and DRAM connections during Initial Program Load (IPL) is
disclosed.  It will run a fast check and detect most open or stuck
conditions as well as some shorted conditions of the data and control
lines to the DRAMs in a memory subsystem.

      Since for many memory subsystems the Dram modules may be
accessed via connectors for field upgradability, the configuration
and connections could be changed before any arbitrary IPL.  It is not
prudent to assume all of the connectors have made contact or that no
components have been blown due to handling of the daughter cards;
therefore, some limited testing is in order.

      The scope of these tests should be as limited as possible while
still covering some of the most obvious failure mechanisms.  An Ideal
test would cover all types of errors associated with the connectors
as well as major component failure such as blown repowering or
multiple DRAM failures.  Faults such as open power pins would also be
covered as they would assert themselves as a multiple DRAM failure.

      Only testing from the memory logic chips to the DRAMs are
necessary.  This is because there are other methods to handle testing
out the logic modules and the connections between them, such as
Built-in Self-Test (BIST) and module controlled wire test.  Other
methods can be used to cover a single DRAM failure or more (Error
Correcting Code (ECC), Redundant modules, etc.).  This allows
comprehensive DRAM testing to be omitted.  Testing for multiple DRAM
failures must be included as multiple modules could have a single
point of failure.

Detail of Ideal Coverage
  Faults to interconnect lines:
  o  Power
  o  Data
  o  Address
  o  Row Address Select
  o  Column Address Select
  o  Output Enable
  o  Read/Write
  o  Toggle
  Types of Faults
  o  Stuck lines
  o  Shorted lines
  o  Open lines
 ...