Browse Prior Art Database

Dual Bidirectional Interposer

IP.com Disclosure Number: IPCOM000115238D
Original Publication Date: 1995-Apr-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 101K

Publishing Venue

IBM

Related People

Droz, TL: AUTHOR [+3]

Abstract

The disclosed interposer permits an Asynchronous Transfer Mode (ATM) adapter processor to access an arbitrated Integrated Command/Data Bus (ICDB) without being explicitly involved in the request and grant arbitration process. The interposer also permits a 16 bit ICDB master to access either 16 or 32 bit wide memory within the adapter processor subsystem without explicitly requesting control. This dual bidirectional interposer resolves the potential deadlock problem associated with the hidden arbitration.

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Dual Bidirectional Interposer

      The disclosed interposer permits an Asynchronous Transfer Mode
(ATM) adapter processor to access an arbitrated Integrated
Command/Data Bus (ICDB)  without being explicitly involved in the
request and grant arbitration process.  The interposer also permits a
16 bit ICDB master to access either 16 or 32 bit wide memory within
the adapter processor subsystem without explicitly requesting
control.  This dual bidirectional interposer resolves the potential
deadlock problem associated with the hidden arbitration.

      This interposer permits information transfers between buses on
an ATM adapter which uses the IBM* Maunakea module for a connection
to the Micro Channel*.  Maunakea provides an ICDB interface for the
adapter side connection.  The interposer supports two way data
transfers between the host processor on the Micro Channel, and the
local processor, an 80960CF, and its memory subsystem on the adapter.
The interposer also provides the local processor with access to frame
data flowing through the adapter.  The position of the interposer
within the adapter is shown in Fig. 1.  The basic control flow for
the interposer is shown in Fig. 2.

      When the local processor addresses the ICDB, the interposer
activates a request to the ICDB arbiter while the processor awaits a
positive acknowledgment of the cycle termination via a READY signal.
When granted access to the ICDB, the interposer becomes a bus master
and drives the read or write cycle onto the ICDB.  The required data
path is established, and on the appropriate clock phase the
interposer terminates both bus transfers.

      When the host processor on the Micro Channel initiates an ICDB
cycle, addressing either DRAM or FLASH of the local processor memory
subsystem, the interposer activates a HOLD to the processor while the
ICDB device awaits removal of the active NOT READY RETURN signal.

When the 80960CF acknowledges with a H...