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Prioritized Shared Bandwidth Channel

IP.com Disclosure Number: IPCOM000115247D
Original Publication Date: 1995-Apr-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 107K

Publishing Venue

IBM

Related People

Cox, FJ: AUTHOR [+2]

Abstract

A logic structure which supports sharing a common bus among multiple, varying bandwith ports is described. All ports can transmit data concurrently, and the shared channel guarantees ports receive an adequate share of the common bus. A simplified version of the design is used to later regenerate individual port data streams from the common channel.

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This is the abbreviated version, containing approximately 52% of the total text.

Prioritized Shared Bandwidth Channel

      A logic structure which supports sharing a common bus among
multiple, varying bandwith ports is described.  All ports can
transmit data concurrently, and the shared channel guarantees ports
receive an adequate share of the common bus.  A simplified version of
the design is used to later regenerate individual port data streams
from the common channel.

      Multiple ports operating synchronously, but with differing
frequencies can share a common channel bus facility.  Each port
interface is 8 bytes wide and the common channel is 16 bytes wide and
feeds into a crosspoint switch.  Thus a port which operates at the
same frequency as the common channel can utilize the common channel
no more than 50 percent.  A port that operates at a fraction of the
frequency of the common channel will utilize a smaller fraction of
the common channel thruput.  Multiple ports of differing frequency
can all share the common channel if 2 conditions are met:
  1.  The sum of the individual port thruputs does not exceed the
       common channel thruput.
  2.  A priority circuit is in place to handle simultaneous requests
by
       different ports to use the shared channel at the same time.

      Fig. 1 shows a dataflow system that allows 2 classes of ports
to share a common channel.  IOP refers to an Input/Output Processor,
and IOA refers to an Input/Output Adaptor which supports attachment
of peripherals.  In this design, the IOP port operates at the common
channel frequency.  The 3 IOA ports operate at 1/4 of the common
channel frequency.  These frequency limits guarantee that the peak
common channel utilization is less than 100 percent.  With the IOA
ports operating at 1/4 the common channel frequency, the common
channel utilization is 1/2 + (3/4)x(1/2) = 7/8.  Other variations
with differing numbers of IOA type ports may be designed in a similar
fashion.  If "N" IOA type ports are required, their frequency must be
1/(N+1) of the common channel frequency or slower to insure that the
channel thruput is not exceeded.

      The IOA ports externally operate on a fixed time division
multiplexed basis as shown in the example.

      The inbound structure shown in Fig. 1 consists of a multiple
stage shift register associated with each p...