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Method of Data Writing to Palette/Digital Analog Converter for Graphics System

IP.com Disclosure Number: IPCOM000115253D
Original Publication Date: 1995-Apr-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Abe, K: AUTHOR [+4]

Abstract

This article describes a data writing method for a graphics system. This method controls the write color look-up table's value from Frame Buffer to Palette/DAC (Digital to Analog converter). Also in this method, CRT refresh data and these register data commonly use Pixel Bus through Frame Buffer to Palette/DAC.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Method of Data Writing to Palette/Digital Analog Converter for Graphics
System

      This article describes a data writing method for a graphics
system.  This method controls the write color look-up table's value
from Frame Buffer to Palette/DAC (Digital to Analog converter).  Also
in this method, CRT refresh data and these register data commonly use
Pixel Bus through Frame Buffer to Palette/DAC.

      Fig. 1 shows the configuration of a conventional graphics
system.  In that system, the DAC register (color look-up tables,
etc.) value are written by the CPU through the CPU I/F Bus and DAC
Bus.  And the CPU should monitor blanking period and write these data
within the blanking period, otherwise the display image is disordered
by this operation.

      In this method, at first, the CPU writes these DAC register
value to Frame Buffer and send command of writing these DAC register
value to the Graphics Processor, then the Graphics Processor controls
to write these data to DAC register from Frame Buffer.  The timing of
the data writing is controlled by the Graphics Processor in Blanking
period through the Pixel Bus.  The Pixel Bus is commonly used by this
DAC register writing operation and CRT refresh operation.  Therefore,
DAC Bus is not necessary in this method.  This configuration is shown
in Fig. 2.