Browse Prior Art Database

VESA Local Bus Arbitration Scheme

IP.com Disclosure Number: IPCOM000115254D
Original Publication Date: 1995-Apr-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 6 page(s) / 206K

Publishing Venue

IBM

Related People

Fuoco, D: AUTHOR [+4]

Abstract

Disclosed is a system arbitration scheme for arbitrating among a CPU, an ISA (Industry Standard Architecture) bus DMA (Direct Memory Access) subsystem including system memory refresh, and up to three VL (VESA Local) bus master adapters in a personal computer. This scheme facilitates the use of the VL bus as a high-performance alternative to the ISA bus for bus master video controllers and for other bus master adapters.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 45% of the total text.

VESA Local Bus Arbitration Scheme

      Disclosed is a system arbitration scheme for arbitrating among
a CPU, an ISA (Industry Standard Architecture) bus DMA (Direct Memory
Access) subsystem including system memory refresh, and up to three VL
(VESA Local) bus master adapters in a personal computer.  This scheme
facilitates the use of the VL bus as a high-performance alternative
to the ISA bus for bus master video controllers and for other bus
master adapters.

      Fig. 1 is a system configuration block diagram of a personal
computer system having an ISA bus, but not supporting VL bus master
adapters.  The system arbiter only arbitrates between the CPU and the
ISA bus DMA subsystem.  The ISA bus DMA subsystem arbitrates between
all of the DMA adapters and system memory refresh.  When the
arbitration scheme between the CPU and the ISA bus DMA subsystem,
called the "I-DMA," wants control of the system, it drives the signal
I-DMA BUS REQUEST active, and the system arbiter then drives the
signal CPU HOLD REQUEST active, forcing the CPU to relinquish control
of the system.  Thus, when the CPU has completed its current bus
cycle, it drives the signal CPU HOLD ACKNOWLEDGE active.  The system
arbiter then drives the signal I-DMA BUS GRANT active to grant
control of the system to the I-DMA, which can then initiate bus
cycles as long as it continues to drive the I-DMA BUS REQUEST signal
active.  When the I-DMA no longer wants control of the system, it
drives this signal inactive, and the system arbiter then drives CPU
HOLD REQUEST inactive, granting control of the system back to the
CPU.  The CPU then drives CPU HOLD ACKNOWLEDGE inactive, resuming the
initiation of CPU bus cycles.

      Fig. 2 is a system configuration block diagram of a personal
computer system additionally supporting up to three VBMs (VL bus
master adapters).  In the absence of an efficient arbitration scheme,
one or more of these five devices may receive insufficient bandwidth
or even no bandwidth.  The presently disclosed arbitration scheme
provides sufficient bandwidth for each device by guaranteeing that
each device is granted control of the system within a specific number
of changes in bus masters and by assuring that a device granted
control of the system will not be preempted until a predetermined
time has elapsed.  The system arbiter arbitrates between all of the
BUS REQUEST signals before granting control of the system to a
specific device.

      The CPU is the default system bus master, which is granted
control of the system when no BUS REQUEST signals are active.  Also,
whenever another device relinquishes control of the system, the
system arbiter samples the CPU BUS REQUEST signal, along with the
other BUS REQUEST signals, to determine which device will be granted
control of the system.  If the system arbiter drives CPU HOLD REQUEST
inactive to grant control of the system to the CPU, the system
arbiter ignores the other BUS REQUEST signals...