Browse Prior Art Database

Power Management Mechanism for Personal Computers

IP.com Disclosure Number: IPCOM000115261D
Original Publication Date: 1995-Apr-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 123K

Publishing Venue

IBM

Related People

Weakley, TL: AUTHOR

Abstract

Described is an implementation to provide a power management mechanism, to personal computers (PCs), so as to conserve power without sacrificing performance.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 45% of the total text.

Power Management Mechanism for Personal Computers

      Described is an implementation to provide a power management
mechanism, to personal computers (PCs), so as to conserve power
without sacrificing performance.

      The implementation uses an initialization program to identify
idle loops within a PC operating system.  When an idle loop is
detected, the power management mechanism will slow the processor
clock.  During this slow clock mode of operation, if the mechanism
detects that the processor wants to execute an instruction that is
outside of an idle loop, it will return the processor clock to full
speed.  In this way, power is conserved since during slow clock
operation power consumption is less.

      The initialization program must be executed immediately after
the operating system is loaded.  The software for the initialization
program includes the following functions:
  1.  The processor's cache is flushed using the "INVD" instruction.
  2.  An OUT instruction is issued that is recognized as a "start
       initialize" command.
  3.  Optional step for additional loops.  An OUT instruction is
issued
       that is recognized as a "continue initialize" command.
  4.  The operating system is put into an idle loop, or sleep
command.
  5.  Optional step for additional loops.  Another idle loop is
       executed, such as DOS Wait for keyboard interrupt.
  6.  An OUT instruction is issued that is recognized as a "stop
       initialize" command.
      a.  If more idle loop conditions require identification, then
           steps 2a and 3a are repeated with 3a causing a different
idle
           loop.

      The initialization commands "start", "continue", and "stop" are
recognized as different addresses within the input/output (I/O)
address space.

      The mechanism contains: a tag cache, that has a depth of 256
entries; and a width of four, that is a four way set associative.
Each entry contains an address tag and a valid bit.  For Intel* i486
processors, which have a sixteen byte L1 cache line, address bits
A11-A4 are used as an offset into the tag cache and address bits
A31-A12 form the tag.  For the Intel* Pentium processors, which have
a 32 byte L1 cache line, address bits A12-A5 are used as an offset
into the tag cache, and address bits A31-A13 form the tag.  When
either the "start initialize" or the "continue initialize" commands
are recognized, all valid bits within the tag cache are reset.  These
bits are not reset when the processor executes an "INVD" instruction.

      The mechanism uses an internal timer to ensure that the idle
loop is executed when the initialization begins.  The internal timer
is set to a large enough value to allow for the operating system to
start the idle loop.  The same timer is also used to determine the
total length of time required to initialize the loop.  Therefore, the
initialization program mus...