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Browse Prior Art Database

Concurrent Central Processor Microcode Updates

IP.com Disclosure Number: IPCOM000115298D
Original Publication Date: 1995-Apr-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 82K

Publishing Venue

IBM

Related People

Gildea, M: AUTHOR [+3]

Abstract

Disclosed is a mechanism for the microcode updates in a multi-processing central processor design which consists of a plurality of Processing Units (PU), Vector Processors (VP) and Dynamic Address Translation (DAT) engines. The microcode updates for all the processors are performed atomically so that instruction processing produces consistent result in computation.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Concurrent Central Processor Microcode Updates

      Disclosed is a mechanism for the microcode updates in a
multi-processing central processor design which consists of a
plurality of Processing Units (PU), Vector Processors (VP) and
Dynamic Address Translation (DAT) engines.  The microcode updates for
all the processors are performed atomically so that instruction
processing produces consistent result in computation.

      Two copies of microcode, one active and one backup copy, for
the PU, VP and DAT engines are maintained in the Service Processor
(SP) DASD and Hardware System Area (HSA) of main memory.  The active
copy is the one that is currently loaded in the control store.  When
the backup copy is updated with new microcode and loaded into the
control store, the backup copy is then switched to the role of the
active copy.  To prepare for microcode updates, the SP loads the
image copy of the updated microcode into the SP DASD and into the
backup copy of HSA while the system is operating normally.  After the
loading of the backup copy into HSA from the SPs DASD, all the
processors are placed in the pipeline hold state such that
instruction processing is soft stopped, and pipeline processing is
installed with clocks still running.  During this Pause state, new
fetches of microcode from the control store for processor execution
are prohibited.

      The Control Store (CS) array is partitioned into a fixed
portion where microcode remains always resident once loaded, and a
pageable or cached portion for less frequently used microcode.
Loading the control store image from HSA of storage is needed to
initialize the fixed portion of CS.  While fixed control store is
being loaded, the control store Directory for the pageable portion of
CS is marked INVALID for all the pages.  Pageable CS is not
initialized but is demand paged as the system requires.

      To initiate a control store load, a special address is scanned
into the Control Store Address Register (CSAR) which contains the
starting address of the updated microcode within the control store
space of HSA.  A maintenance command...