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Set Associative Cache Design using Slow Memory

IP.com Disclosure Number: IPCOM000115301D
Original Publication Date: 1995-Apr-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 75K

Publishing Venue

IBM

Related People

Shimizu, S: AUTHOR

Abstract

This article describes a mechanism to cheaply realize a set associative cache by effectively using slow memory devices. By interleaving a cache line in multiple cache data memory banks which are originally provided for making set associative cache, cache memory interleaving is also realized, and hence, the needed access time for the cache data memory can be relaxed.

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Set Associative Cache Design using Slow Memory

      This article describes a mechanism to cheaply realize a set
associative cache by effectively using slow memory devices.  By
interleaving a cache line in multiple cache data memory banks which
are originally provided for making set associative cache, cache
memory interleaving is also realized, and hence, the needed access
time for the cache data memory can be relaxed.

      The disclosed mechanism has the following advantages; (1) cache
data memory has to be divided into multiple banks which are naturally
required for implementing a set associative cache, and do not have to
be divided into further bunks for interleaving.  Hence, the cache
data memory can be easily constructed, and (2) the needed access time
for the cache data memory can be relaxed as with the case where the
cache data memory is interleaved into multiple-ways.

      In order to relax the required access time for the cache data
memory, memory interleaving technique is commonly used (Fig. 1).  In
Fig. 1, a cache line consisting of from data 0 to data 3 in this case
is interleaved in two-way interleaved data memory.  By interleaving a
cache line like this, the needed access time of the data memory is
relaxed in double, since the interleaved two memory banks can start
to access two consecutive words of the cache line simultaneously for
a cache line burst transfer.  On the other hand, a set associative
cache is implemented by using multiple data banks so that multiple
cache lines...