Browse Prior Art Database

Field Progammable Gate Arrays Based Multibus Development Card

IP.com Disclosure Number: IPCOM000115323D
Original Publication Date: 1995-Apr-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 130K

Publishing Venue

IBM

Related People

Hartley, LF: AUTHOR

Abstract

A method is disclosed for the rapid functional verification of Application Specific Integrated Circuits (ASICs) utilizing a printed circuit board equipped with a matrix of Field Programmable Gate Arrays (FPGAs). The implementation allows for a wide variety of ASIC designs to be functionally verified in true system environments without the need for any additional physical hardware development.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 50% of the total text.

Field Progammable Gate Arrays Based Multibus Development Card

      A method is disclosed for the rapid functional verification of
Application Specific Integrated Circuits (ASICs) utilizing a printed
circuit board equipped with a matrix of Field Programmable Gate
Arrays (FPGAs).  The implementation allows for a wide variety of ASIC
designs to be functionally verified in true system environments
without the need for any additional physical hardware development.

      The hardware described in this publication includes a printed
circuit board, illustrated in the Figure, equipped with 4 field
programmable gate array devices, a general purpose interconnect unit,
a general purpose external interface block and design data memory.
The principle is presented with 4 FPGAs and an interconnect array,
but the reader will note that the idea could be arbitrarily expanded
to incorporate larger arrays of FPGAs and interconnects.

      In an effective implementation, the FPGAs are chosen with large
logic capacity and high I/O count to maximize the logic function
capability of the board.  The breakdown of the interconnect busses (A
through H in the Figure) are chosen to optimize design partitioning
flexibility and FPGA I/O capabilities.  The General Purpose Interface
block takes the form of a generic connector to which specific
external hardware could attach allowing it to interface with the FPGA
logic array.  Such an external pod could take the form of an infrared
transceiver, a radio, a wired communication channel connector or and
audio box to list just a few.  This allows system designers to test
the common function (like the transceiver or radio) with the various
platforms to ensure the design is stable.

      Mechanical Aspects - The unique element to note regarding the
physical board is the mechanical design.  The board is physically
constructed to allow the insertion of the card into any desktop
machine implementing a Micro Channel* or Industry Standard
Architecture (ISA) system bus or any machine which supports the
Personal Computer Memory Card Internation Association (PCMCIA) bus.
In the case of the PCMCIA implementation, the solution is not in the
specified form factor, but as a prototype vehicle this was not the
intention.  The PCMCIA wing can be equipped with a mechanical frame
to ease insertion into the PCMCIA slot.  The Micro Channel and ISA
portions of the card were implemented by identifying the critical
dimensions for 'fitting' in each machine and designing the physical
card layout to conform to the minimum of those dimensions.  The
support for PCMCIA was made possible by notching the corner of the
card (on the Micro Channel side) to create a PCMCIA wing conformant
to the PCMCIA width definition.  This principle could be adapted to
support other physical interface requirements.

      To use the card in an ISA machine, the ISA card edge connector
is inserted into a 16-bit ISA expansion slot.  In the current
e...