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Method to Detect and Correct a Missing Halt Instruction

IP.com Disclosure Number: IPCOM000115334D
Original Publication Date: 1995-Apr-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 6 page(s) / 174K

Publishing Venue

IBM

Related People

Harris, EW: AUTHOR [+2]

Abstract

Disclosed is a method for providing a halt instruction in a battery-powered computer providing Advanced Power Management (APM) capabilities, through an APM device driver, without properly implementing the CPU Idle routine. This routine is used to conserve battery power by halting the processor when the operating system is idle. However, some battery operated computers provide APM capabilities without properly implementing the CPU Idle routine. In such a device, the CPU Idle routine fails to issue the halt instruction.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 39% of the total text.

Method to Detect and Correct a Missing Halt Instruction

      Disclosed is a method for providing a halt instruction in a
battery-powered computer providing Advanced Power Management (APM)
capabilities, through an APM device driver, without properly
implementing the CPU Idle routine.  This routine is used to conserve
battery power by halting the processor when the operating system is
idle.  However, some battery operated computers provide APM
capabilities without properly implementing the CPU Idle routine.  In
such a device, the CPU Idle routine fails to issue the halt
instruction.

      The Advanced Power Management Specification (Version 1.0)
defines a set of power management software routines residing in the
Basic Input/Output System (BIOS) routines of, primarily,
battery-powered computers.  These power management routines are
responsible for monitoring and managing the power usage of the
systems.  A synergy between the operating system and these power
management routines running on battery powered computers can provide
battery savings in addition to the economies which can be achieved by
using power management software operating from BIOS.

      One APM routine, called CPU Idle, is responsible for issuing
the halt (HLT) instruction to put an Intel processor into a halt
state, in which power consumption is reduced, lengthening the time
the computer can operate from battery power without recharging.  When
the CPU Idle routine is called, the scheduler expects the processor
to be halted until the next external hardware interrupt occurs.
However, in a system not properly implementing the CPU Idle routine,
the processor is not halted, and control is immediately returned to
the scheduler.  While the system is idle, the scheduler continuously
requests that the APM device driver issue the CPU Idle function.
This process wastes battery power, since the processor could
otherwise be halted.

      Fig. 1 is a block diagram showing how the OS/2* 2.0 scheduler
directly issues the halt instruction when the system is idle.

      Fig. 2 is a block diagram showing the operation of the OS/2 2.1
scheduler, implementing the OS/2 APM architecture.  The scheduler
determines whether the system has a task ready to run, calling the
APM CPU Idle routine if the system is idle, or the APM CPU Busy
routine before dispatching the next task to run if the system is
busy.  However, the OS/2 scheduler does not call these routines
directly,
calling instead the OS/2 IdleHook routine of the APM device driver,
which in turn calls the APM BIOS CPU Idle and CPU Busy routines.

      The scheduler calls the OS/2 APM device driver at its IdleHook
routine address, passing a parameter specifying whether the device
driver should call the CPU Idle routine or the CPU Busy routine.
When the address of the IdleHook routine is zero, the scheduler knows
that the APM process is not available in the BIOS code of the system,
and issues the halt instruction...