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Orthogonal Data Flow for High-Concurrency in a Digital Signal Processor

IP.com Disclosure Number: IPCOM000115335D
Original Publication Date: 1995-Apr-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 6 page(s) / 229K

Publishing Venue

IBM

Related People

Blaner, B: AUTHOR [+5]

Abstract

The evolution of Digital Signal Processors (DSPs) can be characterized by an increasing concurrency of operations in a single machine cycle. Of course, a high level of concurrency requires a high level of control. Placing all of this control into a single instruction word is a very difficult challenge, and results in certain compromises which can be considered as placing severe restrictions on both the Instruction Set and the Data Flow. Of particular concern in the development of this invention are the restrictions placed upon the Data Flow.

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Orthogonal Data Flow for High-Concurrency in a Digital Signal Processor

      The evolution of Digital Signal Processors (DSPs) can be
characterized by an increasing concurrency of operations in a single
machine cycle.  Of course, a high level of concurrency requires a
high level of control.  Placing all of this control into a single
instruction word is a very difficult challenge, and results in
certain compromises which can be considered as placing severe
restrictions on both the Instruction Set and the Data Flow.  Of
particular concern in the development of this invention are the
restrictions placed upon the Data Flow.

      The Data Flow compromises made in today's existing DSPs can be
grouped into two general areas:
  1.  Data Flows for DSPs may be tailored towards one particular type
       of data.  For instance, Texas Instruments offers several
       "families" of DSPs.  One targets 16-bit Fixed Point data, one
       targets 32-bit Fixed Point data, and another targets Floating
       Point data.  These various families do provide limited
       manipulation of the other data types, but are tailored to one
       particular data type.  Most importantly, these families are
not
       compatible, which means that code written for one must be
       re-written and re-compiled for use on another TI DSP family.
  2.  Registers used for the various concurrent operations tend to be
       grouped into separate register files.  For instance, the
Analog
       Devices 21020 DSP contains five separate register files.  Four
of
       these are used for Data Address Generation, and one is used
for
       Arithmetic operations.  This separation of registers into
       different register files creates a Data Flow which is a poor
       compiler target.  Compilers are most efficient when all the
       registers used for data manipulation are grouped into a
"General
       Purpose Register" (GPR) file.

      The Data Flow described herein does not suffer from these
problems.  It efficiently handles four different types of data, while
at the same time employing a true General Purpose Register file.
This allows it to be applied to a wide range of Multi-media problems:
from Modems, to MPEG, to high-quality audio.  At the same time, it
presents the best compiler target of all Digital Signal Processors
currently on the market.

      The Data Flow described herein was invented during the
development of the Mwave Signal Processor Level 2.0 (MSP-2.0)
Architecture, a signal processor for advanced Multimedia
applications.  The data flow is a major element of the MSP-2.0
Architecture.  One of the most important goals of the MSP-2.0
Architecture Team was to develop an architecture which could be used
across a broad spectrum of signal processing applications, yet still
provide a "coder-friendly" environment for the development...