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Browse Prior Art Database

Unique Implementation for 64-Bit Integer to Floating Conversion

IP.com Disclosure Number: IPCOM000115346D
Original Publication Date: 1995-Apr-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 107K

Publishing Venue

IBM

Related People

Burchfiel, SM: AUTHOR [+3]

Abstract

In a 64-bit processor architecture, there exist requirements to convert a 64-bit integer to a floating point number representation. This invention utilizes the hardware already optimized for a floating multiply add instruction (such as exists in POWER and PowerPC* architectures) to implement the integer to float instruction.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Unique Implementation for 64-Bit Integer to Floating Conversion

      In a 64-bit processor architecture, there exist requirements to
convert a 64-bit integer to a floating point number representation.
This invention utilizes the hardware already optimized for a floating
multiply add instruction (such as exists in POWER and PowerPC*
architectures) to implement the integer to float instruction.

      The integer to float instruction takes a 64-bit signed integer
and performs a conversion to yield a standard IEEE 754 sign magnitude
floating point representation.  The biggest challenge is to get the
63 bits of data of the integer into what is normally a 52-bit data
path the mantissa of the floating point number) and then determining
the proper exponent for the operation.  Fig. 1 shows the format of
the 64-bit integer compared to the standard double precision floating
point representation.

      The PowerPC* 620 made a unique modification to the B alignment
shifter in contrast to the normal B alignment shifter used for the
floating multiply add operation to accommodate this instruction.
Fig. 2 shows the alignment shifter.

      The alignment shifter is split into three levels.  The first
level is a 4-1 mux that shifts from 0 to 3-bit positions to the
right.  Level one creates a 56-bit data path.  The second level is a
4 to 1 mux that essentially performs a nibble shift (a bit shift of
0, 4, 8, or 12 bits).  The shift at the third level is a 6 to 1 mux
that, along with some special connections, performs a 16-bit word
shift (effectively a 96, 112, 128, 144, or 160-bit shift).  This
level effectively creates a 161-bit data path.  Note that since we
normally start with a 53-bit value most of the 161-bit data path is
driven to a constant.

      Fig. 2 also shows how the bits are actually shifted while Fig.
3 shows a basic top level diagram of the mantissa data flow.  The
lower 53 bits of the operand are forced through the first level of
shift by a constant of 12.  The remaining 11 bits of the data (coming
from the exponent data path) are inserted into a section of the
second level that is essentially the...