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Browse Prior Art Database

Modified LOCOS Process

IP.com Disclosure Number: IPCOM000115354D
Original Publication Date: 1995-Apr-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Euen, W: AUTHOR [+2]

Abstract

This article describes a method for reducing the width of an opening in a CVD layer, defined by a photolithographic step.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 73% of the total text.

Modified LOCOS Process

      This article describes a method for reducing the width of an
opening in a CVD layer, defined by a photolithographic step.

      Lateral shrinkage of current DRAM devices for increased cell
integration density is often hindered by photolithographic groundrule
limitations.

      When using the VSLI technology, the electrical isolation
between electrically active cells is often achieved by means of local
oxidation (Field Oxide, LOCOS Process).  In this case windows are
etched into a silicon nitride layer deposited over the whole surface
by means of a photomask.  Subsequently, the exposed parts are
thermally oxidized.  The oxidized areas are broader than those
originally defined by the photomask due to lateral diffusion
(so-called birds beak).  When using a 0.7 &mu.m technology and a
layer thickness of the field oxide of about 350 nm, a minimum oxide
width of about 1.1 &mu.m can be achieved.

      The desired isolation effect of the field oxide is achieved if
a defect free zone having a npn (or pnp) transition is present
beneath the oxide.  The following equation is valid for such a MOS
transistor: V[t] >> operating voltage.

The spacer deposition/dry etch process described herein comprises the
following steps:
  o  pad oxidation
  o  pad nitride deposition
  o  field isolation mask (predefines field oxide areas)
  o  dry etch pad layers (opens field area)
     -  nitride deposition (spacer material)
  o  nitri...