Browse Prior Art Database

Common Front End Bus for High-Performance Chip-to-Chip Communication

IP.com Disclosure Number: IPCOM000115355D
Original Publication Date: 1995-Apr-01
Included in the Prior Art Database: 2005-May-16
Document File: 2 page(s) / 76K

Publishing Venue

IBM

Related People

Ackerman, JE: AUTHOR [+8]

Abstract

Disclosed is a Common Front End (CFE) local bus configured to provide efficient communications among a number of highly-integrated Application-Specific Integrated Circuit (ASIC) chips.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Common Front End Bus for High-Performance Chip-to-Chip Communication

      Disclosed is a Common Front End (CFE) local bus configured to
provide efficient communications among a number of highly-integrated
Application-Specific Integrated Circuit (ASIC) chips.

      Intelligent, high-function adapter cards are often complete
systems including several subsystems.  These subsystems are often
individually implemented as ASIC chips, each of which typically has a
processor, serial communications capability, memory, and unique
interface, such as a Micro Channel* interface, called a back-end
subsystem interface.  However, when communications are established
between subsystems with different interfaces, the performance of one
or more of the subsystems is usually compromised.

      The Figure is a schematic diagram showing how various
subsystems are connected using a CFE local bus to resolve the
performance problems otherwise experienced with the use of the
various unique interfaces of the subsystems.  Each subsystem may be,
for example, an ASIC chip.  This CFE bus is a high-performance,
parallel, synchronous bus allowing fast, efficient chip-to-chip
communications with a minimal number of interface signals.  The CFE
bus architecture is scalable, so that new subsystem ASIC chips fit
into existing designs without modifying the CFE interface.

      For 32-bit components, 32 bits of address are multiplexed with
32 bits of data, as parity support is provided for both address and
data.  At ADDRESS (ADS) time, BYTE ENABLES (-BE0-3) and WRITE_READ
(+W/-R) are driven by the master.  No parity is associated with these
signals.  For 64-bit components, 32 bits of address and 8 control
bits (-BE0-7) are multiplexed with 64 bits...