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High Performance Impedance Controlled CMOS Driver

IP.com Disclosure Number: IPCOM000115356D
Original Publication Date: 1995-Apr-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 103K

Publishing Venue

IBM

Related People

Gregor, RP: AUTHOR

Abstract

Disclosed is a design for a CMOS output impedance controlled driver which provides good impedance and slew-rate control without sacrificing driver delay. Delay is minimized by avoiding use of series resistors or long channel output devices to control the output impedance as used in previous designs. Instead, the driver accepts process dependent digital inputs into a unique circuit arrangement to minimize delay.

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High Performance Impedance Controlled CMOS Driver

      Disclosed is a design for a CMOS output impedance controlled
driver which provides good impedance and slew-rate control without
sacrificing driver delay.  Delay is minimized by avoiding use of
series resistors or long channel output devices to control the output
impedance as used in previous designs.  Instead, the driver accepts
process dependent digital inputs into a unique circuit arrangement to
minimize delay.

      There have been previous CMOS driver designs that have used
process dependent digital inputs to control only the driver output
impedance, the following disclosed circuit shown below goes a step
further and controls both the output impedance and switching slope
(slope control) of the driver.  Furthermore, the circuit structure is
optimized to provide the highest performance possible.

      The driver as shown in the figure is a tristate impedance
controlled driver.  The output devices are Q23P, Q24P, Q25P, Q23N,
Q24N, and Q25N.  Q23P and Q23N are sized to give the correct output
impedance when the process is near the best case conditions (highest
gain FETs).  Q24P and Q24N are sized to get the correct output
impedance in parallel with Q23P and N when the process is near
nominal.  Q25P and Q25N are sized to provide the correct output
impedance in parallel with the Q23 and Q24 transistors when the
process is near the worst case conditions (lowest gain FETs).

      Each output FET is controlled by a separate predriver so that
the speed of the drive can be controlled by the process dependent
inputs C1 and C2.  Under best case conditions, both C1 and C2 are
logic zero (gnd).  At nominal conditions, C1 = logic 1, and C2 =
logic 0.  At worst case conditions, both C1 and C2 are logic 1.  The
D input is the Data input, and the E input is the tristate enable
input.  Since, the predrive networks for Q23N, Q24N, and Q25N are
exact logical duals of the predrive networks for Q23P, Q24P, and
Q25P, I will only describe the Q23P through Q25P predrivers.

      The basic predriver approach is that as each process control
input (C1 and C2) becomes active, another output device is enabled,
and the previously enabled predrivers...