Browse Prior Art Database

3-State Decoder for External 3-State Buffer

IP.com Disclosure Number: IPCOM000115367D
Original Publication Date: 1995-Apr-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Fukuta, M: AUTHOR

Abstract

Disclosed is a circuit for adding an external 3-state buffer. This circuit decodes a 3-state signal to two digital signals. One is a control signal, another is an input signal to external buffer. These two signals drive an external 3-state buffer.

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3-State Decoder for External 3-State Buffer

      Disclosed is a circuit for adding an external 3-state buffer.
This circuit decodes a 3-state signal to two digital signals.  One is
a control signal, another is an input signal to external buffer.
These two signals drive an external 3-state buffer.

      Fig. 1 shows the circuit configuration.  The level setting
circuit (1) changes the 3-state signal (A) of Fig. 2 to three levels
signal (B) of Fig. 2.  The window comparator (2) detects the middle
value or high impedance state then outputs a control signal (C) of
Fig. 2.  The external 3-state buffer (3) of Fig. 2 can make a
buffered 3-state signal which is same as signal (A) of Fig. 2.

      The level setting circuit sets the middle value to high level
for the external buffer if the 3-state signal is active low.  If the
3-state signal is active high, the middle value is set to low level
for the 3-state bufer.