Browse Prior Art Database

Method for Reduction in Memory Requirements Via Tag Bit Replication

IP.com Disclosure Number: IPCOM000115382D
Original Publication Date: 1995-Apr-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 105K

Publishing Venue

IBM

Related People

Hovis, WP: AUTHOR [+4]

Abstract

A method to reduce memory requirements in systems with a tag bit is disclosed. The reduction is accomplished by replicating the tag bit on the bus to/from memory so that each dataflow chip receives a copy of the information. The data is not stored in each dataflow chip for each transfer, but is stored in an alternating fashion so that the tag bit is equally shared among all dataflow chips. On the processor side of the bus, when the tag bit is driven from memory only one dataflow chip is sending valid tag data. All copies received are logically 'ORed' together to form the tag bit. Dataflow chips that don't have the valid tag drive out a logical '0' to allow this to function as stated.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Method for Reduction in Memory Requirements Via Tag Bit Replication

      A method to reduce memory requirements in systems with a tag
bit is disclosed.  The reduction is accomplished by replicating the
tag bit on the bus to/from memory so that each dataflow chip receives
a copy of the information.  The data is not stored in each dataflow
chip for each transfer, but is stored in an alternating fashion so
that the tag bit is equally shared among all dataflow chips.  On the
processor side of the bus, when the tag bit is driven from memory
only one dataflow chip is sending valid tag data.  All copies
received are logically 'ORed' together to form the tag bit.  Dataflow
chips that don't have the valid tag drive out a logical '0' to allow
this to function as stated.

      Certain systems' data requirements include a Tag bit per Double
Word (DW) (8 bytes) of data.  This bit is stored with the data to
indicate the status of the DW to software (i.e., modified or
unmodified).  For purposes of the memory subsystem, the bit is
treated like all other data bits and is included in the memory Error
Correcting Code (ECC).  With system size and bus widths increasing,
multiple components are used in conjunction to transfer data to and
from main memory.  Current structures have resulted in Full Word (FW)
(4 byte) slices of data from multiple data chips forming the data bus
back to the processor (Fig. 1).  In our case, systems can be built
with the components such that each segment is from a different chip,
or so that two segments are generated from one chip.  This type of
structure caused us to develop systems that used some data chips with
no Tag bit and others that had a Tag bit with each transfer to the
processor.  Multiple bus transfers would then be used to form the
data stored to the Dynamic Random Access Memory (DRAM) arrays.  This
division required that all data chips and DRAM arrays behind them be
able to accommodate a Tag bit per FW.  The full ECC word then
consisted of two bus transfers of data and tag along with an address
parity bit, a redundant bit, and the check bits (32 data, 1 tag, 32
data, 1 t...