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New Redundancy Architecture for Array Macros

IP.com Disclosure Number: IPCOM000115398D
Original Publication Date: 1995-Apr-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 6 page(s) / 179K

Publishing Venue

IBM

Related People

Cantiant, T: AUTHOR [+3]

Abstract

Large memories are designed with redundant word lines selected by fuses to replace damaged word lines. For each selection into the array, the current address is compared to redundant addresses. Upon the result of this comparison, the word line or the redundant world line is selected. This operation takes place into the "critical path" of the memory. Faster is this operation, faster the access time of the array is. Word addresses are compared to fuse addresses. In case of multiple redundant word lines, to select only one redundant word line another fuse input must be introduced. This input is called "FUSE ENABLE". There are as many fuses enable input as redundant word lines. The conventional solution illustrated in Fig.

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New Redundancy Architecture for Array Macros

      Large memories are designed with redundant word lines selected
by fuses to replace damaged word lines.  For each selection into the
array, the current address is compared to redundant addresses.  Upon
the result of this comparison, the word line or the redundant world
line is selected.  This operation takes place into the "critical
path" of the memory.  Faster is this operation, faster the access
time of the array is.  Word addresses are compared to fuse addresses.
In case of multiple redundant word lines, to select only one
redundant word line another fuse input must be introduced.  This
input is called "FUSE ENABLE".  There are as many fuses enable input
as redundant word lines.  The conventional solution illustrated in
Fig. 1 requires 3 logic stages: MUXES to compare addresses and fuses
(bit by bit), then a NOR controlled by a fuse which determine the
redundant WL (FUSES ENABLE) and finally, a logical OR to disable all
the decoders when a redundant word line has been activated.

      This article discloses a new way to implement a redundant path
into an array with the minimum impact on performance in order to
improve the access time.

      The new approach is fully dynamic allowing an improvement in
access time and cycle time as well a total control between addresses
and clocks.  As static MUXES are suppressed, and using a new pulsed
NOR approach, clocks allowing the beginning of the logical operation
are generated earlier in the cycle, improving the cycle time.  The
second stage is composed by a pulsed NOR.  Setted to the redundancy
mode, data cross the circuit in a flush mode whithout the gating of
the clock, which means a fast delay.  The timing analysis given below
compare a classical approach to the new one.  Boxes size is a image
of the delay.  For a dynamic circuit, a safety delay is introduced
before the capture of the data by the clock to insure that only
correct data can be captured.  The new approach will be described by
reference to Figs. 2 and 3.

      This new way to implement redundancy path consists in a pulsed
NOR by a clock (CLK1).  Fuses information and current address are now
compared into the input of the NOR.

      The NOR function is set to a logical "1" (set RDT and RDB
nodes), which corresponds to precharge the redundancy path to a
"fail" mode, (i.e., the current address is the same that the
redundant address).

      As soon as the current address is generated, a positive pulse
on CLK1 enable the logical operation.  The comparison can be done by
the couples (current address versus fuse address).  If at least, one
of the logical values of the fuses is identical to a bit address, the
NO redundant mode is activated (no fail).  In fact, there is a path
to GND, RDT or RDB falls down and RDD goes up, which enable the
"normal" Decoder.  To check all the combinations, Address/fuse and
Complementary add/ Complementary fuse c...