Browse Prior Art Database

Programmable Interface Receiver

IP.com Disclosure Number: IPCOM000115408D
Original Publication Date: 1995-Apr-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 108K

Publishing Venue

IBM

Related People

Granato, MA: AUTHOR

Abstract

The disclosed design is a programmable receiver latch configuration which increases both the range of cycle times over which a multiple cycle interface will operate, and the cycle time variation tolerance at many cycle times over the range of operation.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Programmable Interface Receiver

      The disclosed design is a programmable receiver latch
configuration which increases both the range of cycle times over
which a multiple cycle interface will operate, and the cycle time
variation tolerance at many cycle times over the range of operation.

      The design of interfaces between functional units has become
increasingly critical as system operating cycle times have been
reduced.  Multiple cycles of data are being stored on these
interfaces to compensate for the faster machine speeds.  An "n" cycle
interface design requires the minimum delay for the path to be "n-1"
cycles, and the maximum delay to be "n" cycles, and as "n" increases
for a given interface design, the range of operable system cycle
times is reduced.

      A significant improvement of the cycle time operating range,
and the tolerance to cycle time variation at a given cycle time, can
be realized through the use of the Programmable Interface Receiver
(PIR) shown in Fig. 1.  The design configuration is implemented on
the receiving end of an interface, although it could be implemented
on the driving end of an interface in a similar configuration to
achieve comparable results.

      The design incorporates 2 latches, which have different clock
sources, and a selector which determines whether the interface data
is to be captured directly at latch B, or whether the staged data in
latch A is passed to B.  Latch B is driven by the same clocks used by
the downstream logic to synchronize the interface with the subsequent
logic.  Latch A is driven from an independent clock source, operating
at the same system frequency as the clocks for latch B, and has the
capability to easily modify its output clock arrival times so that it
may be offset from the latch B clocks.  The selector gate is a signal
which is also easily modified, and functions to maintain a value
determined by the timing of the interface to ensure the interface
data is properly captured in latch B for subsequent processing.  The
modification of the clock arrival time, and the selector gate, is
accomplished with programmed logic which chooses a predetermined
setting based on the operating cycle time, however there are simpler
approaches which can achie...