Browse Prior Art Database

Cycle-Driven Pattern Generator with Cycle Offset

IP.com Disclosure Number: IPCOM000115457D
Original Publication Date: 1995-May-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 106K

Publishing Venue

IBM

Related People

Clark, RA: AUTHOR

Abstract

In efforts to increase throughput rates on high performance memory cards, many card designs incorporate instruction overlap which allows the card to begin its next instruction while completing the current one.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Cycle-Driven Pattern Generator with Cycle Offset

      In efforts to increase throughput rates on high performance
memory cards, many card designs incorporate instruction overlap which
allows the card to begin its next instruction while completing the
current one.

      Cycle-based memory testers have a tough time implementing this
feature especially when trying to fit refresh instructions in between
these overlapping instructions.  Traditional tester limitations
require that the programming of all signals to and from the card for
any particular instruction must line up on the same starting and
ending cycle.  The design disclosed here removes that limitation.

      The pattern generator design is shown in Fig. 1.  Inputs to
this card are:
  Next Address Field       this provides the address of the next
                            control word to execute
  Next Cycle Count         this provides the number of cycles this
next
                            control word will take to execute
  Cycle Clock              which drives the counters in a
synchronized
                            manner relative to other pattern
generators
                            in the system.

      Expect for the clock, the inputs are relatively low frequency.
A new Next Address and Next Cycle Count are provided to the card once
per instruction which may be many cycles.  The design benefits from
receiving these inputs as soon as possible before the next
instruction (or control word) is to execute.

Each generator receives 2 fields from the Control RAM:
  SAR       Starting Address Register which provides the beginning
             point in the Pattern RAM for the current instruction.
Both
             generators can share this field.
  OFFSET    Cycle Offset value which is separate for each.  This is a
             signed value to allow pre or post offset operation.

      The cycle offset function is contained in the timing counter
logic shown in Fig. 1.  As each instruction executes the cycle
counter decrements then reloads the Next Cycle Count after it counts
to zero.  This counter provides the reference point for all timing
generators within the system.

      Once the SAR is loaded in to the Pattern Counters, they
increment through the Pattern RAM providing a desired sequence of
patterns to the product at cycle speeds.  The control for loading the
counter with the next SAR is handled by a cycle comparitor.  This
comparitor is what provides the generator the ability to start its
product instruction patterns either earlier or later with respect to
the cycle counter reference.

      If the OFFSET field is left at zero, then all instructions
start in th...