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Asynchronous Signal Sample Circuit without Racing

IP.com Disclosure Number: IPCOM000115469D
Original Publication Date: 1995-May-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Ioki, K: AUTHOR [+2]

Abstract

Disclosed is an asynchronous signal sample method which can remove racing condition. The circuit consists of two levels of flip-flops. First level flip-flops receive asynchronous signals directly. The combinational logic which generate the input to second level flip-flops is designed to remove racing condition. As a result, the output of second level flip-flops does not contain racing condition.

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Asynchronous Signal Sample Circuit without Racing

      Disclosed is an asynchronous signal sample method which can
remove racing condition.  The circuit consists of two levels of
flip-flops.  First level flip-flops receive asynchronous signals
directly.  The combinational logic which generate the input to second
level flip-flops is designed to remove racing condition.  As a
result, the output of second level flip-flops does not contain racing
condition.

      The circuit structure is shown in Fig. 1.  REG1 are first level
flip-flops and receive DATA_IN signals which can include any number
of signals and are supposed to be asynchronous against CLOCK.  REG2
are second level flip-flops and provide the output of this circuit
named DATA_OUT.  The input to REG2 depends on the value of REG1_OUT
which is the output of REG1 and the value of DATA_OUT.  If REG1_OUT
and DATA_OUT have the same value, then REG2_IN which is the input to
REG2 are provided with REG1_OUT.  Otherwise REG2_IN is provided with
DATA_IN.  When the bit width of the DATA_IN is one, this circuit
works as hazard remove logic as shown in Fig. 3.  As illustrated in
this timing chart, there is a possibility for REG1 to sample a
hazard, but it disappears in REG2.  If the bit width of the DATA_IN
is more than one, this circuit removes racing states which does not
appear on DATA_IN.  Fig. 4 shows the example when the bit width is
two.  As DATA_IN changes around the rising edge of CLOCK, REG1_OUT
con...