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Serial Port Register Write/Read Circuit without Restriction on Clock Count

IP.com Disclosure Number: IPCOM000115479D
Original Publication Date: 1995-May-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 107K

Publishing Venue

IBM

Related People

Yasuda, T: AUTHOR

Abstract

Disclosed is a circuit for register write/read operation with serial port without constraint on clock count. The two independent clocks enable this - one is for temporary shift register to communicate external module and the other is for actual write operation to register array.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Serial Port Register Write/Read Circuit without Restriction on Clock
Count

      Disclosed is a circuit for register write/read operation with
serial port without constraint on clock count.  The two independent
clocks enable this - one is for temporary shift register to
communicate external module and the other is for actual write
operation to register array.

      Fig. 1 shows the register write/read timing of I/O signals in
this circuit.  This circuit ignores extra clocks for register data
write/read.  It is useful because preparing exact number of clocks is
not easy in high frequency.  In this circuit, address and data share
one address/data line.  Therefore there are five I/O lines -
Address/Data Line, two Clock Lines Write/Read Enable Line and Power
On Reset Line.  Fig. 2 shows the whole structure of the circuit.
"REGISTER WRITE/READ CLOCK"(A) and "CRYSTAL CLOCK"(B) are independent
clocks.  The frequency of the CLOCK (A) is less than one-third that
of the CLOCK (B).  The CLOCK (A) drives two shift registers.  The two
"SHIFT REGISTER"s (SRW is for write and SRR is for read) store data
temporarily to implement serial write/read operation.

      The structure of "WRITE CLOCK CONTROL LOGIC" is shown in
Fig. 3.  It consists of three portions (a),(b) and (c).  The circuit
portion (a) is synchronous with the CLOCK (A) while the circuit
portion (b) works with the CLOCK (B).

      Fig. 4 shows the timing of this circuit.  Binary counter counts
up the CLOCK (A) after the release of "POWER ON RESET" signal and the
activation of "ENABLE" signal....