Browse Prior Art Database

Clock Gating of Upgrade Socket

IP.com Disclosure Number: IPCOM000115481D
Original Publication Date: 1995-May-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Carpenter, GD: AUTHOR [+3]

Abstract

Disclosed is a means to disable the three clocks to the upgrade socket in a desktop PowerPC* system when no upgrade is installed.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 80% of the total text.

Clock Gating of Upgrade Socket

      Disclosed is a means to disable the three clocks to the upgrade
socket in a desktop PowerPC* system when no upgrade is installed.

      The desktop PowerPC system must provide three high-speed clocks
to the upgrade socket.  If the upgrade socket is unused, the three
clocks
generate unnecessary electromagnetic noise and planar power
consumption.

      The presence bits on the power-up upgrade interface
(L2_PRESENT* and 60X_PRESENT*, which are active low and indicate the
presence of an L2 cache or upgrade processor) are used to drive the
output enable of the clock distribution chip.  This allows the three
clocks to the upgrade socket to be disabled when no upgrade is
present in the socket.  The presence bits are pulled low by each
upgrade card and have a light pull-up on the planar to present a high
to the logic when no upgrade is present.

      This implementation is used for a planar requiring three system
planar clocks and three upgrade clocks.  It utilizes a multi-output
oscillator chip like the IBM* PN 51G7780 with outputs that can be
disabled using control inputs to the oscillator chip.  For this chip,
the control inputs are the 2's complement Big-Endian encoding of the
number of outputs that are active (e.g. EN0,1,2=101 enables outputs
1-3 and EN0,1,2=101 enables outputs 1-6).  These control inputs are
driven by the presence bits from the upgrade interface via logic
shown in the Figure.

      With this ...