Browse Prior Art Database

Double Dense Cache Directory, Implemented in an Embedded Array Polar Masterslice

IP.com Disclosure Number: IPCOM000115485D
Original Publication Date: 1995-May-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 91K

Publishing Venue

IBM

Related People

Holt, J: AUTHOR [+7]

Abstract

Disclosed is a design, and a new design method, developed to produce a directory chip, via an automated system Electronic Design Automation (EDA), for a double dense cache design required for systems development. Previous to this development, bipolar directory chips were implemented as custom designed chips.

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Double Dense Cache Directory, Implemented in an Embedded Array Polar
Masterslice

      Disclosed is a design, and a new design method, developed to
produce a directory chip, via an automated system Electronic Design
Automation (EDA), for a double dense cache design required for
systems development.  Previous to this development, bipolar directory
chips were implemented as custom designed chips.

      An embedded array design, and directory design process, was
developed to make possible the development of the next generation air
cooled Thermal Conduction Module (TCM) system.  Aggressive
performance objectives over the previous system's design pushed the
expansion of the cache to twice its size, which caused the directory
to be doubled as well, yet no chip locations were available on the
TCM for the additionally required directory chips.  Power dissipation
of the TCM was increasing due to performance changes also, thus
limiting any power increases on the existing directory design's
chip-sites, in addition, the development schedule and budget,
precluded that new custom directory chips could not be a viable
alternative.

      In response to this need a very low power, yet high
performance, embedded array was developed (Fig. 1), utilizing a small
storage cell, and designed to fit into the available chip areas of a
Masterslice (MS) chip.  A design method was then developed, so that
four of these arrays could be hand placed in the MS chip design
(Figs. 2 and 3),...