Browse Prior Art Database

Carry Prediction for Exponent Underflow Detection

IP.com Disclosure Number: IPCOM000115488D
Original Publication Date: 1995-May-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 127K

Publishing Venue

IBM

Related People

Dao Trong, S: AUTHOR [+4]

Abstract

In a floating point pipeline processor the result of a floating point addition/subtraction has to be normalized, i.e., shifted left to eliminate any leading zero digits. Accordingly, the exponent has to be reduced by the number of digit positions shifted. When the resulting exponent becomes smaller than the lower exponent range, an exponent underflow occurs. Depending on a control mask there are two ways to respond to such result. First, the result is set to zero. Simultaneously, the condition code is set to zero and any data feed-back path will be set to zero. Second, the result is understood as an exponent underflow exception. In this case an exception flag is set and all further instructions are cancelled. Simultaneously, the processing pipeline will be cleared.

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Carry Prediction for Exponent Underflow Detection

      In a floating point pipeline processor the result of a floating
point addition/subtraction has to be normalized, i.e., shifted left
to eliminate any leading zero digits.  Accordingly, the exponent has
to be reduced by the number of digit positions shifted.  When the
resulting exponent becomes smaller than the lower exponent range, an
exponent underflow occurs.  Depending on a control mask there are two
ways to respond to such result.  First, the result is set to zero.
Simultaneously, the condition code is set to zero and any data
feed-back path will be set to zero.  Second, the result is understood
as an exponent underflow exception.  In this case an exception flag
is set and all further instructions are cancelled.  Simultaneously,
the processing pipeline will be cleared.  Due to the plurality of
processing steps required for the appropriate response, the detection
of an exponent underflow condition becomes crucial for the
performance of the floating point process, especially when there are
many data bypasses and feedback paths as in case of a deep pipeline
processor architecture.  The result mantissa has to be examined digit
by digit to check for high order zero digits.  In accordance with the
result of this check a shift operation has to be performed to shift
out the high order zero digits of the mantissa.  An encoder network
converts the number of digits shifted out into a four-bit number
which is then subtracted from the exponent to deliver the final
result exponent and in parallel an exponent underflow indication
signal.  In case of a 64-bit mantissa adder and a 9-bit exponent
adder the encoder takes five logic stages and the exponent adder
takes 9 logic stages to generate the result which in the whole means
a delay of 14 stages.  The critical path to generate the exponent
underflow indication signal includes the 64-bit adder, the encoder
logic and the 9-bit adder.

      This drawback can be avoided by a circuit arrangement
comprising a carry look ahead logic connected to the mantissa adder
and a carry select logic connected to the output of the exponent
adder where the output of the former controls a multiplexer which is
part of the carry select logic.

      Because the shift amount is only 4-bit wide, an exponent
underflow indication depends on the carry-out in the fifth bit
position of the mantissa adder.

      The result bits C(0).....  C(4), are either A(0)  ....  A(4),
unchanged or A(0) ... A(4), reduced by 1 depending on the carry-out
in the bit position A(4).  Herein bit C(0) is the exponent underflow
indication signal.

      To detect the carry-out in bit position A(4) the lowest 4 bits
A(5) ... A(8) of the exponent are decoded into 15 single signals
which indicate that the lower 4 bits are greater or equal to 1,2,3
.... 15.  Such decoding is not time critical.  A carry-out in bit
position A(4) will be generated when:
  wherein E...