Browse Prior Art Database

N-Level Hierarchical Grouping Scheme for Placing Chip Components

IP.com Disclosure Number: IPCOM000115496D
Original Publication Date: 1995-May-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Bolliger, MD: AUTHOR

Abstract

Disclosed is a process to hierarchically group and modify chip components for generating the components placement coordinates. Each defined group can consist of chip components and other groups with features such as mirroring about the x or y axis, rotation about an origin, and other options. The process supports n-levels of hierarchy.

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N-Level Hierarchical Grouping Scheme for Placing Chip Components

      Disclosed is a process to hierarchically group and modify chip
components for generating the components placement coordinates.  Each
defined group can consist of chip components and other groups with
features  such as mirroring about the x or y axis, rotation about an
origin, and other options.  The process supports n-levels of
hierarchy.

      The designer defines groupings of chip components that can
contain other groups by specifying the components instance names
inbetween 'begin group' and 'end group' markers and gives the group
an unique 'name'.  The components can be grouped either horizontally
or vertically; can each be individually mirrored about an axie or
rotated; the entire group can be justified by any of the four corners
of the minimum bounding box comprising all components; in addition to
other useful features.

      In addition the designer can designate the creation of power
busses, routing wires, spacings inbetween components, the
interpretation of the component ordering, etc with the ability to add
more features as needed.

      The n-level hierarchical grouping scheme assists the designer
in helping to solve three main factors in chip floorplanning.  In
addition, an automated placement tool can be invoked on certain
levels and partitions in the hierarchy to optimize for other
constraints (e.g., wiring).

      The first factor is obtaining the chip performan...