Browse Prior Art Database

Memory Map for a Desktop PowerPC System

IP.com Disclosure Number: IPCOM000115511D
Original Publication Date: 1995-May-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 137K

Publishing Venue

IBM

Related People

Bui, HQ: AUTHOR [+6]

Abstract

Disclosed is a memory map for a desktop PowerPC* system using the PowerPC 601* processor.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Memory Map for a Desktop PowerPC System

      Disclosed is a memory map for a desktop PowerPC* system using
the PowerPC 601* processor.

      The desktop PowerPC system design does not utilize the
programmed I/O (PIO) function available in the PowerPC architecture
due to cost and performance considerations.  An alternate I/O scheme
is therefore required.  The memory-mapped I/O scheme disclosed here
provides an effective, low-cost solution.

      The PowerPC 601 processor has a 4-GB address space.  The
desktop system interfaces the processor to a PCI bus which has 4-MB
memory, 4-GB I/O, and 4-GB configuration spaces.  The desktop system
must also support cycles to Flash ROM.

Fig. 1 illustrates the 601 bus cycle translations.
  o  Cycles initiated by the processor will be forwarded to system
      memory with no address change if the address is less than 2 GB.
  o  Contiguous or Non-Contiguous I/O Mode is selected by setting a
      bit in the I/O Type Register.
  o  All 601 cycles with addresses above 2 GB will be run to the PCI
      with high-order address bits A/D 31,30 set to zero.  Except as
      noted, addresses from 2 GB to 3 GB cause PCI I/O cycles to be
      generated, while addresses from 3 GB to 4 GB cause PCI memory
      cycles to be generated.  Address lines are passed in the order
of
      significance except as specially mapped in some regions noted
      below:
     -  A 601 address in the top 8 MB will cause a ROM cycle to run.
         This may not be a PCI cycle, but it uses the A/D lines.
     -  For Contiguous I/O Mode, a 601 address in the first 8 MB
         above 2 GB will cause an I/O cycle to run on the PCI with
the
         low 30 address bits unchanged.  The low 64 KB of addresses
         are forwarded to the ISA bus if not claimed by a PCI agent.
         Thus, for example, 601 Address 8000 0102 maps to Port 0102.
        -  For Non-Contiguous I/O Mode, a 601 address in the first 8
MB
            above 2 GB will cause an I/O cycle to run on the PCI, and
a
            special address translation is done so that the 8 MB
space is
            compressed into 64 KB of PCI addresses (0 - 64 KB).  All
I/O
            cycles with PCI addresses below 64 KB are forwarded to
the
            ISA bus by the system I/O (SIO), if they are not claimed
by a
            PCI agent.  In this mode the 601 cannot create PCI I/O
            addresses between 64 KB and 8 MB - 1.
        -  601 addresses between 2 GB + 8 MB and 2 GB + 16 MB cause
PCI
            configuration cycles to run.
        -  601 addresses from 3 GB - 8 MB to 3 GB do n...