Browse Prior Art Database

PCMCIA Interrupt Multiplexing

IP.com Disclosure Number: IPCOM000115518D
Original Publication Date: 1995-May-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Peterson, JC: AUTHOR [+3]

Abstract

Disclosed is a means to prevent PCMCIA interrupt conflicts in a PowerPC* system.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 97% of the total text.

PCMCIA Interrupt Multiplexing

      Disclosed is a means to prevent PCMCIA interrupt conflicts in a
PowerPC* system.

      The desktop PowerPC system uses a PCMCIA controller chip that
uses interrupt steering as a means of addressing an interrupt
request.  This steering technique steers the interrupt request from
the PC card to one of the I/O system bus interrupt request lines (IRQ
3, 4, 5, 7, 9, 10, 11, 12, 14 and 15).  This form of interrupt
handling
could cause interrupt conflicts due to the system interrupt
requirements.

The disclosed invention resolves this problem by multiplexing:
  o  I/O interface signals (A/B: IOWR; IORD),
  o  Reset signals (A/B: RESET),
  o  Attribute Memory Select (A/B: REG*),
  o  Interrupt Request (A/B: IREQ),
  o  Functional Interrupt Request (INTR*) and
  o  System Reset Drive (ISA_RESET_DRV)
  by decoding these signals using a programmable logic device,
   outputting a single interrupt request signal to an I/O position
dip
   switch.  This interrupt request line is connected to all I/O
A-side
   positions of the switch, whereas the Y-side is connected to the
I/O
   system bus interrupt request lines.

      This solution makes the adapter non-system-specific in respect
to the interrupt level it must use.  The switching makes the IRQ line
enabled or disabled at the AT-bus.  When the switch is set to ON, the
IRQ level is then connected to the bus.

      The Figure shows the invention's implementatio...