Browse Prior Art Database

Enhanced 72-Pin Single Inline Memory Module Package

IP.com Disclosure Number: IPCOM000115532D
Original Publication Date: 1995-May-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 154K

Publishing Venue

IBM

Related People

Fusco, R: AUTHOR [+2]

Abstract

By using Identification and Presence Detection (ID and PD) bits and mechanical keying plus redefinition of some pins, usefulness of standard 72-bit Single Inline Memory Module (SIMM) packaging is extended to safely include several advanced devices.

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This is the abbreviated version, containing approximately 53% of the total text.

Enhanced 72-Pin Single Inline Memory Module Package

      By using Identification and Presence Detection (ID and PD) bits
and mechanical keying plus redefinition of some pins, usefulness of
standard 72-bit Single Inline Memory Module (SIMM) packaging is
extended to safely include several advanced devices.

      The standard 72-pin SIMM package described in JEDEC Standard
No.21-C of The Electronic Industries Standard is modified to allow
addition of the following capabilities:
  1.  Memory densities of 64MB and 128MB using 64Mb (3.3V devices).
  2.  Support for Hyper Page Mode DRAMs.
  3.  Support for Low Power/Self Refresh DRAMs (3.3V and 5V).
  4.  Support for 3.3V DRAMs.
  5.  Support for x8 and x9 DRAMs.

Selection of these new features includes use of both PD and ID bits.
Provision is made for data widths shown below:
  x32 (Non-parity): No parity bits.
  x36 (Parity):      4 parity bits.
  x36 (ECC):        36 data bits

Changes from JEDEC Standard 21-C are as follows:
  1.  Memory densities of 64 MB and 128 MB using 64MB (3.3V) devices:
       A new address (A12) is assigned to pin 33, which was a Row
       Address Select (RAS) input.  Although the current 72-pin
parity
       SIMM has 4 RAS inputs (2 per 16/18 bits), this new SIMM family
is
       optimized for use with 4-byte (or wider) memory busses.  This
       prevents the use of the new assembly in systems requiring an
       interleaved 2-byte buss.  This change also provides
compatability
       with Quad Column Address Select (CAS) devices.  Quad CAS
devices
       are not useable in interleaved 2-byte applications since the
       parity bits are shared across 4 bytes.
        Table 1 is a pinout summary that includes existing 72-Pin
       SIMM pin definitions found in JEDEC Standard 21-C and changes
       made for the new SIMM.  Abbreviations used in the tables are
       standard in the industry.
  2.  Support for Hyper Page Mode (HPM) DRAMs - An additional PD pin
is
       added to differentiate Hyper Page Mode devices from Fast Page
       Mode (FPM).  Pin 66...