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Browse Prior Art Database

Protocol for Asynchronous System Error Reporting in a PowerPC System

IP.com Disclosure Number: IPCOM000115536D
Original Publication Date: 1995-May-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Curry, SE: AUTHOR [+3]

Abstract

Disclosed is a means to report asynchronous system errors to the CPU in a desktop PowerPC* system.

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Protocol for Asynchronous System Error Reporting in a PowerPC System

      Disclosed is a means to report asynchronous system errors to
the CPU in a desktop PowerPC* system.

      In a PowerPC system, system error conditions may occur
asynchronously to the CPU.  These errors must be reported to the CPU
in a manner that is predictable.  Examples of such conditions are:
Non-Maskable Interrupt (NMI) on an ISA expansion bus, or an L2 cache
data parity error that is not detected while a CPU cycle is in
progress.

      The solution implemented in the desktop PowerPC system is for
the

PCI

Bridge

and Memory Controller control chip to assert an
external interrupt to the CPU when an asynchronous system error is
detected, regardless of the cycle in progress.  This interrupt will
cause the CPU to initiate an interrupt acknowledge cycle.  The
control chip will then terminate the interrupt acknowledge with a
Transfer Error Acknowledge (TEA) and put 0xFF on each data byte lane.
This will cause the CPU to enter its TEA handler and perhaps
diagnostics to determine the nature of the system error.

      If an external interrupt was already pending before the system
error was detected, the control chip will assert TEA# on the first
interrupt acknowledge cycle run initiated by the CPU.  The INT line
(external interrupt) will then be reasserted for the still-pending
external interrupt.
  *  Trademark of IBM Corp.