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Power-On Self Test and Diagnostic Functions for Differential Small Computer System Interface Applications

IP.com Disclosure Number: IPCOM000115543D
Original Publication Date: 1995-May-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 6 page(s) / 227K

Publishing Venue

IBM

Related People

Buckland, PA: AUTHOR [+3]

Abstract

Disclosed is an interface by which a sixteen-bit Small Computer System Interface (SCSI) chip having the ability, in normal operation, to act as both a target and an initiator can control external differential transceivers. With this interface, the chip can arbitrate, select, or reselect itself, and can then conduct information and asynchronous data transfers, testing its own Input/Output (I/O) circuits and the I/O circuits of the external differential transceivers to which it is connected.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 43% of the total text.

Power-On Self Test and Diagnostic Functions for Differential Small
Computer System Interface Applications

      Disclosed is an interface by which a sixteen-bit Small Computer
System Interface (SCSI) chip having the ability, in normal operation,
to act as both a target and an initiator can control external
differential transceivers.  With this interface, the chip can
arbitrate, select, or reselect itself, and can then conduct
information and asynchronous data transfers, testing its own
Input/Output (I/O) circuits and the I/O circuits of the external
differential transceivers to which it is connected.

      During Power-On Self Test (POST) and diagnostic tests, this
interface provides a method to test the differential transceiver
control and I/O signal bus, along with the internal SCSI functions of
the SCSI interface chip.  In a test/diagnostic mode, a set of
registers in this chip completes the nexus with the functional
hardware through the external transceivers, which are also connected
to the differential transceivers.  The Test Mode Register (h'40'),
the FIFO Test Data Register, and the SCSI Parity Register (h'48') are
manipulated  by the microprocessor in order to emulate the other
device in the nexus.

      Fig. 1 is a table listing the definitions of I/O signals and of
differential transceiver control signals of the interface.

      Fig. 2 is a table listing the definitions of the Test Mode,
FIFO Data Test, and SCSI Signal Test registers of the SCSI interface
chip.

      Fig. 3 is a table listing the definitions of the SCSI Data Test
and SCSI Parity registers of the SCSI interface chip.

      An example of a scenario for using the test registers to put
the chip in test mode and to verify both the internal functions of
the chip and the interconnections with external differential
transceivers.  For this example, the functional logic in the chip has
been programmed to arbitrate, select its own ID, send a message byte,
and send a command byte.  The functional logic arbitrates by
activating +S_ENBSY, and the +S_ENDB(0:15) and -S_DB(0:15)
corresponding to its own ID.  The external differential transceivers
will in turn drive the +BSY and -BSY, and the +DB(0:15) and -DB(0:15)
pair for its ID.  The device must activate only the enable and 1/O
signals to its own differential transceiver so that it will still be
able to monitor the other IDs on the bus.  The functional logic
detects a "win" and waits for any other arbitrating devices to
release their signals.  The functional logic selects itself by
driving +S_ENBSY, +S_ENINIT, -S_SEL, -S_ATN, only its ID (one pair of
-S_DB(0:15) and +S_ENDB(0:15), +S_ENDBP and the correct parity bit
(-S_DBP or -S_SDBP1), and then releases +S_ENBSY.  All of these
signals cause the corresponding signals on the SCSI side of the
differential transceivers to switch states.

      The microprocessor monitors -S_BSYI, -S_SELI, -S_ATN, and its
own ID by means of the SCSI BSY,...