Browse Prior Art Database

Addressing of Storage Operands with Variable Field Length

IP.com Disclosure Number: IPCOM000115549D
Original Publication Date: 1995-May-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 151K

Publishing Venue

IBM

Related People

Getzlaff, K: AUTHOR [+3]

Abstract

CISC computer architectures usually provide instructions for operations with one or two storage operands which may start at any arbitrary byte address and have a variable field length each. The operand addresses reference to a virtual storage divided into pages with a typical size of 4 kilobyte. During processing of the operands it must be assured that the translation from the virtual address to the real address has been completed and that the operands are available in the physical storage even though the operands may cross page boundaries. Usually this is done before the start of the instruction execution. If during execution of the instruction a page miss occurs, i.e., a page not available in the physical storage, a restore of the initial parameters and data is required.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 43% of the total text.

Addressing of Storage Operands with Variable Field Length

      CISC computer architectures usually provide instructions for
operations with one or two storage operands which may start at any
arbitrary byte address and have a variable field length each.  The
operand addresses reference to a virtual storage divided into pages
with a typical size of 4 kilobyte.  During processing of the operands
it must be assured that the translation from the virtual address to
the real address has been completed and that the operands are
available in the physical storage even though the operands may cross
page boundaries.  Usually this is done before the start of the
instruction execution.  If during execution of the instruction a page
miss occurs, i.e., a page not available in the physical storage, a
restore of the initial parameters and data is required.  This is
necessary to resume or restart the instruction after the addresses
are
resolved and the addressed data are available in the physical
storage.

      Another difficulty arises if the operand length depends on an
end character in the operand field or if the completion of an
instruction
depends on the match of two operands.  In such cases an indication is
needed whether a page boundary is crossed or not.  No access to the
new
page will be allowed if the operand ends in the old page.

      Another performance problem is caused by the variable byte
address if a word or double word crossing occurs in a cache memory.
In this case two consecutive cache accesses are required.  The
performance can be improved if one operand is aligned to the word or
doubleword boundary with the first access.  A reduced access field
length is calculated in a previous step and is used for the first
access of both operands.  The following cache accesses extend over
the full word or double word length depending on the dataflow width.

      The arrangement shown in Figs. 1 and 2 improves the performance
of the such addressing operations by reducing cache accesses during
the execution of instructions for processing storage operands with
variable length.  The arrangement provides that the first access to
fetch operand 1 from the cache is performed by an address of a
reduced field length aligned to the dataflow width.  The same field
length is used for the first access of operand 2.  The field length
of operand 1 addressed in the first access corresponds to the smaller
value of (1) the dataflow width, (2) the difference between the
address of the first byte of operand 1 and the dataflow width or (3)
the residual length in a length count register.  The address
calculation for operand 2 follows the same scheme as explained above
for operand 1.  Since the address of operand 2 cannot be aligned, two
accesses to the cache must be accepted.  The address determination is
performed during the cache access and does not need previous
calculations.

      The length count register 12 (Figs. 1 and 2) is se...