Browse Prior Art Database

Stacked Memory Modules

IP.com Disclosure Number: IPCOM000115559D
Original Publication Date: 1995-May-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Qureshi, A: AUTHOR [+2]

Abstract

Today's systems and application software require even increasing memory. The density of memory chips has increased from 64K to 16M and will increase to 64M chips in near future. In spite of this 1000X increase in memory density, there is a continuing effort to package these chips into smaller space and volume because present day SIMM cards take significant space on CPU planars.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 77% of the total text.

Stacked Memory Modules

      Today's systems and application software require even
increasing memory.  The density of memory chips has increased from
64K to 16M and will increase to 64M chips in near future.  In spite
of this 1000X increase in memory density, there is a continuing
effort to package these chips into smaller space and volume because
present day SIMM cards take significant space on CPU planars.

      One way to reduce planar space taken by memory is to utilize 3D
packages.  Many solutions have been proposed and are being developed
by companies like TI, Irwine Sensors and StakTak.  Theses packages
are
based on stacking of bare chips into 3D stacks and require
development
of new fabrication processes.  The disclosed concept also provides a
3D
structure but is based on technology that is being used now.

      The concept uses a multi-chip-module approach.  Fig. 1 shows
one package type where memory chips are assembled on both sides of a
carrier substrate.  The carrier provides an array of I/O pads that
can be connected to another substrate carrier through a series of
compliant contact elements.  Many carriers can be thus stacked on top
of each other.  The electrical interconnection is accomplished when a
clamping force is applied to the top of the stack.

      A similar 3D structure can be provided by using a double-sided
module interconnect interposer.  In this scheme the chip carrier has
I/O pins in place of pads.  Module interconn...