Means To Utilize PCI Level-Sensitive Interrupts within an ISA-PC Edge-Sensitive Environment
Original Publication Date: 1995-May-01
Included in the Prior Art Database: 2005-Mar-30
Dean, ME: AUTHOR [+3]
Disclosed is a means to utilize PCI level-sensitive interrupts within ISA-based edge-sensitive systems.
Means To Utilize PCI Level-Sensitive Interrupts within an
a means to utilize PCI level-sensitive interrupts
within ISA-based edge-sensitive systems.
desktop system relies on the use of an ISA
expansion bus to access a vast array of peripheral cards. The system
also uses a PCI bus that defines interrupts as level-sensitive, which
is incompatible in an ISA-based environment.
PowerPC system, this problem is resolved with an
interrupt system based on a chip containing two interrupt
controllers. The system assigns devices to interrupts in an
industry-compatible manner in order to simplify porting available
code to the PowerPC processor.
assignments result in a certain number of interrupts
being available for use on both expansion slot types. PCI defines up
to four interrupts (A, B, C, D) per slot, which are far too many.
When a PCI
slot is not occupied, the corresponding interrupt is
available to ISA cards. Auto configuration cards will see a low
level and not automatically utilize these interrupts.
connected to IRQ9 (interrupt request) or IRQ11 are
not affected by this mechanism. The software may or may not issue
EOI9 (end of interrupt) or EOI11 when servicing an ISA card connected
to one of these levels, and the only effect may be to delay the next
interrupt by approximately 500 ns.
achieves its objectives of allowing PCI cards to
operate in an edge-sensitive environment and allowing ISA devices to
use interrupts to unoccupied slots.
illustrates the interrupt connections for one PCI
slot. The dotted lines indicate a variation on the invention. With
the variation, the pull-down resistor...