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Circuit Technique for Optimizing Access Time in Static Random Access Memories

IP.com Disclosure Number: IPCOM000115577D
Original Publication Date: 1995-May-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 6 page(s) / 284K

Publishing Venue

IBM

Related People

Correale Jr, A: AUTHOR [+2]

Abstract

Classically, the access time of an Static Random Access Memories (SRAM) is determined by the slowest transition (low-to-high or high-to-low) of the output data signals with respect to the positive going edge of the clock. Typically, in CMOS technologies, the slowest output transition is the low-to-high transition where the output port is trying to drive a large capacitance from ground to Vdd. The output stage is generally comprised of a "pull-up" PFET through which the output load capacitance is charged. Since PFETs generally have poorer current carrying capability when compared against a comparable NFET, the rising transitions are always the center of performance issues.

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Circuit Technique for Optimizing Access Time in Static Random Access
Memories

      Classically, the access time of an Static Random Access
Memories (SRAM) is determined by the slowest transition (low-to-high
or high-to-low) of the output data signals with respect to the
positive going edge of the clock.  Typically, in CMOS technologies,
the slowest output transition is the low-to-high transition where the
output port is trying to drive a large capacitance from ground to
Vdd.  The output stage is generally comprised of a "pull-up" PFET
through which the output load capacitance is charged.  Since PFETs
generally have poorer current carrying capability when compared
against a comparable NFET, the rising transitions are always the
center of performance issues.  This disclosure describes a circuit
configuration, closely combining the sense amplifiers and the output
latch and utilizing the fact that the sense amplifier outputs are
always precharged to Vdd volts ('one').  Through considering the
sense amplifier and the latch as a system, the circuit configuration
will take advantage of the precharged state of Vdd volts, when the
data being read is a logic 'one' or Vdd volts, by immediately passing
the level to the latch and therefore to the output, without having to
wait for the sense amplifier to resolve the state of the bitlines.
In addition, the set-up and hold-times for the output latch are no
longer a concern since the latch clock and the sense amplifier enable
are the same signal.

      A typical SRAM array consists of bit columns made up of memory
cells, a write driver, a sense amplifier, and an output latch.  Fig.
1
illustrates the block diagram of such a bit column.  Word line
address decoders, located outside the array, provide the word line
enable signal  to the corresponding word line in the array during a
Read or Write operation.  Since the scope of this disclosure concerns
itself with optimizing the access times of an SRAM, the Read
operation will be the focus of the following discussion.

      A Read operation is outlined by the following sequence.  The
appropriate word line is enabled (through the decoding of the
address) and the contents of the cells are made available on a pair
of bitlines Read Bitline True (RBLT) and Read Bitline Complement
(RBLC).  These bitlines are always kept at a precharged voltage of
'Vdd' when the RAM is not active i.e., no "Read or Write" operation
in progress, by a bitline restore circuit not illustrated in Fig. 1.
Therefore, during a Read enabled cells will discharge on e of the bit
lines in the pair, depending on the state of the cell.  This
discharging will develop a differential voltage between the bitlines
which is fed to a sense amplifier.  The sense amplifier will detect
the difference, amplify it and feed its output to a latch.
Therefore,
at the end of the Read cycle the output latches should contain the
data
which was stored in the selected element in the array.

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