Browse Prior Art Database

Cache Memory Structure for Tolerating Faults

IP.com Disclosure Number: IPCOM000115607D
Original Publication Date: 1995-May-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 82K

Publishing Venue

IBM

Related People

Bowen, NS: AUTHOR

Abstract

A high-performance cache memory structure is proposed that achieves fault tolerance by replicating only the modified portions of the cache in a special purpose memory unit (herein called a cache-log). If the primary cache memory is lost then the data is recovered by using the main memory system and the cache-log to reconstruct the data at the time of the failure.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Cache Memory Structure for Tolerating Faults

      A high-performance cache memory structure is proposed that
achieves fault tolerance by replicating only the modified portions of
the cache in a special purpose memory unit (herein called a
cache-log).  If the primary cache memory is lost then the data is
recovered by using the main memory system and the cache-log to
reconstruct the data at the time of the failure.

      This cache memory structure allows a greater fault tolerance
than traditional error coding techniques.  The cache contains a
control section and data section that would be found in a standard
cache.  The cache is modified with a new component called a cache-log
as shown in the Figure.

      The cache log contains three major areas.  A Log Buffer is a
bank of (N) memory words that are accessed in a circular fashion.  A
Current register contains the address of the last location that was
used in the Log Buffer (ranges from 0 to N-1).  This register is
incremented before each access (modulo N).  A Oldest register
contains the address of the oldest valid entry in the circular
buffer.

      For example, assume the Log Buffer has five words (addressed
0,1,,,4) and current=1 and oldest=3.   Then a reverse time ordering
of the data would be contained in locations 1,0,4 and 3.  Location 2
would have no information.

      The cache-log reacts to two types of events.  The first type
records all stores that are made to the memory.  The data plus the
address must be recorded in the Log Buffer.  Some address bits can be
omitted depending on the size of the data and the boundary of the
store (e.g., if 4 bytes are always recorded and based on four byte
boundary then the low two bits can be dropped from the address).  The
second type of information recorded is when a modified cache line is
moved from the cache memory to the main memory.  This is used during
recovery to invalidate any prior stores to the data that may be in
the Log...